公开(公告)号：US20230317691A1

公开(公告)日：2023-10-05

申请号：US18207699

申请日：2023-06-09

申请人： Murata Manufacturing Co., Ltd.

发明人： Takashi IWAMOTO

IPC分类号： H01L25/10 ,  H01L23/498 ,  H01L23/14 ,  H01L23/00

CPC分类号： H01L25/105 ,  H01L23/49827 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/147 ,  H01L24/08 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/08245 ,  H01L2224/16245 ,  H01L2224/29147 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2924/141

摘要： An electronic device includes a substrate, a base substrate, a metal connection body, a metal body, and a via. The substrate includes a first main surface provided with functional elements and is a piezoelectric substrate or a compound semiconductor substrate. The substrate is mounted on the base substrate such that a second main surface of the substrate opposite to the one main surface faces the base substrate. The metal body is provided at the first main surface of the substrate and includes at least a portion that extends to outside the substrate in plan view from the one main surface. The via connects the portion of the metal body outside the substrate and the base substrate to each other and has a higher thermal conductivity than the substrate.

公开(公告)号：US20230282633A1

公开(公告)日：2023-09-07

申请号：US18298104

申请日：2023-04-10

申请人： Kioxia Corporation

发明人： Junichi SHIBATA

IPC分类号： H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/18 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/32054 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/80203 ,  H01L2224/83139 ,  H01L2224/83203

摘要： A semiconductor device has a first substrate including an element region, a peripheral region that surrounds the element region, a first insulator with a first recess portion in the peripheral region, a first metal layer in the element region, and a first conductor in the peripheral region to surround the element region. A second substrate has an element region, a peripheral region that surrounds the element region, a second insulator with a second recess portion that faces the first recess portion, a second metal layer in contact with the first metal layer, and a second conductor that surrounds the element region of the second substrate.

公开(公告)号：US20230154882A1

公开(公告)日：2023-05-18

申请号：US17975218

申请日：2022-10-27

申请人： FUJI ELECTRIC CO., LTD.

发明人： Ryotaro TSURUOKA

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/29 ,  H01L24/83 ,  H01L21/4878 ,  H01L23/49844 ,  H01L23/49866 ,  H01L2924/35121 ,  H01L2224/48225 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/3201 ,  H01L2224/32059 ,  H01L2224/3207 ,  H01L2224/32112 ,  H01L2224/32111 ,  H01L2924/1011 ,  H01L2224/32245 ,  H01L2224/83203 ,  H01L2224/8384 ,  H01L23/3736

摘要： A semiconductor device includes: a semiconductor base body; a semiconductor chip; a sintering material layer bonded to a lower surface of the semiconductor chip and having a thickness decreasing toward an outer periphery of the semiconductor chip; and a conductive plate having a main surface facing the lower surface of the semiconductor chip and a recessed portion which the sintering material layer contacts in the main surface, the recessed portion having a depth decreasing toward the outer periphery of the semiconductor chip.

公开(公告)号：US20230145182A1

公开(公告)日：2023-05-11

申请号：US17984502

申请日：2022-11-10

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Hitoshi Ito ,  Kenichi Koi

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L25/065 ,  H01L21/48

CPC分类号： H01L23/49844 ,  H01L24/32 ,  H01L25/074 ,  H01L25/0657 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/4985 ,  H01L21/4839 ,  H01L21/4825 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2924/30107 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2225/06562

摘要： A semiconductor device includes: a first semiconductor element; a second semiconductor element; a first insulating base member adhesively bonded to the first semiconductor element; a first wiring connected to a first electrode of the first semiconductor element, and disposed on the first insulating base member; a second insulating base member adhesively bonded to the second semiconductor element, a second wiring connected to a third electrode of the second semiconductor element, and disposed on the second insulating base member; a first wiring member connected to a second electrode of the first semiconductor element; a second wiring member electrically connected to the first wiring and a fourth electrode of the second semiconductor element; and a third wiring member connected to the second wiring. A current flows in a first direction in the first wiring member, and flows in a second direction opposite to the first direction in the third wiring member.

公开(公告)号：US20180068972A1

公开(公告)日：2018-03-08

申请号：US15811542

申请日：2017-11-13

申请人： ROHM CO., LTD.

发明人： Shoji YASUNAGA

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L23/31

CPC分类号： H01L24/73 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/2733 ,  H01L2224/29034 ,  H01L2224/32057 ,  H01L2224/32059 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4554 ,  H01L2224/48011 ,  H01L2224/4805 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/78303 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

摘要： A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm.

公开(公告)号：US09837373B2

公开(公告)日：2017-12-05

申请号：US15370436

申请日：2016-12-06

申请人： ROHM CO., LTD.

发明人： Shoji Yasunaga

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L23/31

CPC分类号： H01L24/73 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/2733 ,  H01L2224/29034 ,  H01L2224/32057 ,  H01L2224/32059 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4554 ,  H01L2224/48011 ,  H01L2224/4805 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

摘要： A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm.

公开(公告)号：US20170084569A1

公开(公告)日：2017-03-23

申请号：US15370436

申请日：2016-12-06

申请人： ROHM CO., LTD.

发明人： Shoji YASUNAGA

IPC分类号： H01L23/00 ,  H01L23/495

CPC分类号： H01L24/73 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/2733 ,  H01L2224/29034 ,  H01L2224/32057 ,  H01L2224/32059 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4554 ,  H01L2224/48011 ,  H01L2224/4805 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

摘要： A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm.

公开(公告)号：US20150236003A1

公开(公告)日：2015-08-20

申请号：US14404099

申请日：2012-09-14

申请人： Jumpei Konno ,  Takafumi Nishita ,  Kenji Sakata ,  Nobuhiro Kinoshita ,  Michiaki Sugiyama ,  Tsuyoshi Kida ,  Yoshihiro Ono

发明人： Jumpei Konno ,  Takafumi Nishita ,  Kenji Sakata ,  Nobuhiro Kinoshita ,  Michiaki Sugiyama ,  Tsuyoshi Kida ,  Yoshihiro Ono

IPC分类号： H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/07 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/27312 ,  H01L2224/27334 ,  H01L2224/2741 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/29012 ,  H01L2224/29015 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/753 ,  H01L2224/75315 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83001 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8321 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/83906 ,  H01L2224/83907 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/11 ,  H01L21/304 ,  H01L2224/03 ,  H01L21/78 ,  H01L2221/68381 ,  H01L21/4825 ,  H01L2224/27 ,  H01L2924/01047

摘要： A method of manufacturing a semiconductor device obtained by laminating a first semiconductor chip and a second semiconductor chip with different planar sizes when seen in a plan view on a wiring board via an adhesive material, in which the second semiconductor chip with a relatively larger planar size is mounted on the first semiconductor chip with a relatively smaller planar size. Also, after the first and second semiconductor chips are mounted, the first and second semiconductor chips are sealed with resin. Here, before sealing with the resin, a gap between the second semiconductor chip and the wiring board is previously sealed with the adhesive material used when the first and second semiconductor chips are mounted.

摘要翻译： 一种制造半导体器件的方法，所述半导体器件通过层叠具有不同平面尺寸的第一半导体芯片和第二半导体芯片的方法，所述半导体器件和第二半导体芯片在通过粘合材料在布线板上的平面图中看到，其中具有相对较大的平面尺寸 以相对较小的平面尺寸安装在第一半导体芯片上。 此外，在安装第一和第二半导体芯片之后，用树脂密封第一和第二半导体芯片。 这里，在用树脂密封之前，当安装第一和第二半导体芯片时，使用所使用的粘合剂材料预先密封第二半导体芯片和布线板之间的间隙。

公开(公告)号：US20150102507A1

公开(公告)日：2015-04-16

申请号：US14511158

申请日：2014-10-09

申请人： Samsung Electronics Co., Ltd.

发明人： Cheol-woo LEE ,  Ji-han KO

IPC分类号： H01L23/00

CPC分类号： H01L24/32 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06135 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/3201 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/32053 ,  H01L2224/32056 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4886 ,  H01L2224/48866 ,  H01L2224/48881 ,  H01L2224/48884 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83856 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/8546 ,  H01L2224/92147 ,  H01L2224/92165 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/06 ,  H01L2924/10161 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/13091 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/14511 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/066 ,  H01L2924/05442 ,  H01L2224/83

摘要： Provided is a semiconductor package that may prevent deformation of stacked semiconductor chips and minimize a semiconductor package size. The semiconductor package includes a package base substrate, a lower chip stacked on the package base substrate, an upper chip stacked on the lower chip, and a first die attach film (DAF) attached to a bottom surface of the upper chip to cover at least a portion of the lower chip. The first DAF may be a multi-layer film including a first attaching layer contacting the bottom surface of the upper chip and a second attaching layer attached to a bottom of the first attaching layer to cover at least a portion of a side surface of the lower chip.

摘要翻译： 提供了可以防止堆叠的半导体芯片的变形并使半导体封装尺寸最小化的半导体封装。 半导体封装包括封装基底基板，堆叠在封装基底基板上的下部芯片，堆叠在下部芯片上的上部芯片，以及附接到上部芯片的底表面上的至少覆盖的第一芯片附着膜（DAF） 下部芯片的一部分。 第一DAF可以是多层膜，其包括接触上芯片的底表面的第一附着层和附接到第一附着层的底部的第二附着层，以覆盖下层的侧表面的至少一部分 芯片。

公开(公告)号：US20140306338A1

公开(公告)日：2014-10-16

申请号：US14159813

申请日：2014-01-21

申请人： ADVANCED MICRO DEVICE CO., LTD. (SHANGHAI)

发明人： I-Tseng Lee ,  Yi Hsiu Liu

IPC分类号： H01L23/00

CPC分类号： H01L24/17 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1356 ,  H01L2224/16113 ,  H01L2224/16221 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17134 ,  H01L2224/17179 ,  H01L2224/17515 ,  H01L2224/17517 ,  H01L2224/26125 ,  H01L2224/26155 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29019 ,  H01L2224/2919 ,  H01L2224/3201 ,  H01L2224/32057 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/07025 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

摘要： The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer. The structure and method of present invention at least provide more strength and stress buffer to resist die warpage and absorb thermal cycling stress, and then prevents the bump and dielectric materials in the die-die stacking structure from cracking caused by thermal stress or external mechanical stress.

摘要翻译： 本发明涉及模片堆叠结构及其制造方法。 模片堆叠结构包括具有底表面的顶模，覆盖顶模的底表面的第一绝缘层，具有顶表面的底模，覆盖底模顶表面的第二绝缘层， 顶模和底模之间的多个连接构件和第一绝缘层与第二绝缘层之间的保护材料。 多个连接构件将顶模与底模连通。 保护材料桥接多个连接构件以在第一绝缘层和第二绝缘层之间形成网格布局。 本发明的结构和方法至少提供更多的强度和应力缓冲以抵抗模翘曲并吸收热循环应力，然后防止模芯堆叠结构中的凸起和介电材料由热应力或外部机械应力引起的破裂 。