公开(公告)号：US20130200533A1

公开(公告)日：2013-08-08

申请号：US13795811

申请日：2013-03-12

Applicant: Invensas Corporation

Inventor： Ellis Chau ,  Reynaldo Co ,  Roseann Alatorre ,  Philip Damberg ,  Wei-Shun Wang ,  Se Young Yang

IPC: H01L23/00

CPC classification number: H01L24/85 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49517 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/16 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48997 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/851 ,  H01L2224/8518 ,  H01L2224/85399 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1715 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y10T29/49149 ,  Y10T29/49151 ,  H01L2224/45664 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

公开(公告)号：US08482134B1

公开(公告)日：2013-07-09

申请号：US12917185

申请日：2010-11-01

Applicant: Robert Francis Darveaux ,  Roger D. St. Amand ,  Vladimir Perelman

Inventor： Robert Francis Darveaux ,  Roger D. St. Amand ,  Vladimir Perelman

IPC: H01L23/488

CPC classification number: H01L23/49816 ,  H01L21/50 ,  H01L23/36 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A stackable package is placed within a mold during an encapsulation operation. A compliant surface, e.g., of a compliant film, of the mold is pressed down on upper interconnection balls of the stackable package to force upper portions of the upper interconnection balls into the mold. However, lower portions of the upper interconnection balls are exposed within a space between the compliant surface and a substrate of the stackable package. The space is filled with a dielectric material to form a package body. The package body is formed while at the same time exposing the upper portions of upper interconnection balls from the package body in a single encapsulation operation. By avoiding selective removal of the package body to expose the upper interconnection balls, the number of operations as well as cost to manufacture the stackable package is minimized.

Abstract translation: 在封装操作期间，将可堆叠的封装放置在模具内。 模具的顺应性表面（例如柔顺膜）的柔顺表面被压在可堆叠包装的上互连球上，以将上互连球的上部部分压入模具中。 然而，上互连球的下部暴露在顺应性表面和可堆叠包装的基底之间的空间内。 空间填充有电介质材料以形成封装体。 同时，在单个封装操作中同时形成封装主体，同时将上互连球的上部从封装主体露出。 通过避免选择性地去除封装体以暴露上互连球，操作的数量以及制造可堆叠封装的成本最小化。

公开(公告)号：US20130168857A1

公开(公告)日：2013-07-04

申请号：US13616890

申请日：2012-09-14

Applicant: Thomas Matthew GREGORICH ,  Andrew C. CHANG ,  Tzu-Hung LIN

Inventor： Thomas Matthew GREGORICH ,  Andrew C. CHANG ,  Tzu-Hung LIN

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.

Abstract translation: 本发明提供一种模制插入器封装及其制造方法。 模制插入器封装包括多个金属螺柱。 模制材料封装离开暴露的金属螺柱的底表面的金属螺柱。 第一芯片设置在模制材料上，连接到金属螺柱的顶表面。 多个焊球连接并接触到金属螺柱的底表面。

公开(公告)号：US08476772B2

公开(公告)日：2013-07-02

申请号：US12953812

申请日：2010-11-24

Applicant: Byung Tai Do ,  Arnel Trasporto ,  Linda Pei Ee Chua ,  Reza A. Pagaila

Inventor： Byung Tai Do ,  Arnel Trasporto ,  Linda Pei Ee Chua ,  Reza A. Pagaila

IPC: H01L23/48

CPC classification number: H01L24/14 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10175 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8114 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/0665 ,  H01L2224/05099 ,  H01L2924/00 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires.

Abstract translation: 半导体器件具有形成在基底基板的第一表面中的凹部的基底基板。 第一导电层形成在第一表面上并进入凹槽中。 在基底基板的第二表面上形成第二导电层。 第一半导体管芯安装到基底基板上，凸起部分设置在第一导电层的凹槽内。 第二半导体管芯安装到第一半导体管芯。 在第二半导体管芯和第一导电层之间的基底衬底的第一表面上形成接合线。 密封剂沉积在第一和第二半导体管芯和基底衬底上。 基底基板的一部分从第二导电层之间的第二表面移除到凹部，以形成用于凸块和接合线的电隔离的基底引线。

公开(公告)号：US20130154080A1

公开(公告)日：2013-06-20

申请号：US13326090

申请日：2011-12-14

Applicant: Byung Tai Do ,  Arnel Senosa Trasporto ,  Linda Pei Ee Chua

Inventor： Byung Tai Do ,  Arnel Senosa Trasporto ,  Linda Pei Ee Chua

IPC: H01L23/36 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L23/4334 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead; forming an interior conductive layer having an interior top side and an interior bottom side, the interior bottom side directly on the lead; mounting an integrated circuit over the lead, the integrated circuit having an inactive side and an active side; forming an encapsulation directly on the inactive side and the interior top side; and forming an insulation layer directly on the active side and a portion of the interior bottom side.

Abstract translation: 一种集成电路封装系统的制造方法，包括：形成引线; 形成具有内部顶侧和内底侧的内部导电层，内部底侧直接在引线上; 将集成电路安装在引线上，该集成电路具有无效侧和有源侧; 直接在非活动侧和内侧顶侧形成封装; 以及直接在活性侧和内底侧的一部分上形成绝缘层。

公开(公告)号：US08466567B2

公开(公告)日：2013-06-18

申请号：US12884134

申请日：2010-09-16

Applicant: DaeSik Choi ,  SangMi Park ,  Oh Han Kim

Inventor： DaeSik Choi ,  SangMi Park ,  Oh Han Kim

IPC: H01L23/28

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/11003 ,  H01L2224/1133 ,  H01L2224/13082 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48155 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Abstract translation: 一种制造集成电路封装系统的方法，包括：在连接载体的载体顶侧上形成具有基底器件焊盘和基底互连焊盘的连接载体; 将基座集成电路连接到基座装置焊盘并安装在载体顶侧上; 将底座垂直互连直接安装在基底互连焊盘上; 将基底封装衬底附接到基底集成电路并直接在基底垂直互连上; 在基底封装衬底，基底器件焊盘和基底互连焊盘上形成基底封装; 以及使用与基底封装衬底相对部分地露出的基底器件焊盘和基底互连焊盘去除连接载体的一部分。

公开(公告)号：US08461669B2

公开(公告)日：2013-06-11

申请号：US12886350

申请日：2010-09-20

Applicant: Eric Yang ,  Jinghai Zhou ,  Hunt Hang Jiang

Inventor： Eric Yang ,  Jinghai Zhou ,  Hunt Hang Jiang

IPC: H01L23/52

CPC classification number: H01L23/49575 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/451 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85439 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.

Abstract translation: 公开了一种用于实现开关模式功率转换器的集成电路。 所述集成电路至少包括具有电安静表面的第一半导体管芯，用于控制堆叠在具有所述电气安静表面的所述第一半导体管芯上的所述第一半导体管芯的操作的第二半导体管芯和用于支撑所述第一半导体 将所述第一和第二半导体管芯电连接并电耦合到外部电路。

公开(公告)号：US08441112B2

公开(公告)日：2013-05-14

申请号：US12896283

申请日：2010-10-01

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC: H01L23/02 ,  H01L21/44

CPC classification number: H01L25/50 ,  H01L22/22 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/08145 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01029 ,  H01L2924/07802 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014

Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires.

Abstract translation: 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括：主要部分，包括第一和第二层部分; 以及多个第一和第二端子，其分别设置在主要部分的顶表面和底表面上，并且电连接到多个导线。 第一和第二端子通过使用第一和第二层部分的电极形成。 层叠芯片封装通过层叠两个子结构（其中包括多个预备层部分的阵列），然后切割层状子结构而制造层状子结构来制造。 分层子结构包括多个初级线，其布置在两个相邻的预分离主体之间并且将成为多根线。

公开(公告)号：US20130105966A1

公开(公告)日：2013-05-02

申请号：US13281534

申请日：2011-10-26

Applicant: Amit Subhash Kelkar ,  Karthik Thambidurai ,  Viren Khandekar ,  Hien D. Nguyen

Inventor： Amit Subhash Kelkar ,  Karthik Thambidurai ,  Viren Khandekar ,  Hien D. Nguyen

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/014

Abstract: An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.

Abstract translation: 公开了一种集成电路器件，其包括半导体衬底和附接到半导体衬底的管芯。 导电柱连接到半导体衬底或裸片中的至少一个。 在模具上的半导体衬底上模制包覆模塑，并且导电柱延伸通过包覆模制。

公开(公告)号：US08426981B2

公开(公告)日：2013-04-23

申请号：US13240048

申请日：2011-09-22

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC: H01L23/48 ,  H01L23/02 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/96 ,  H01L21/6835 ,  H01L24/06 ,  H01L24/24 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03011 ,  H01L2224/0346 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1064 ,  H01L2924/07802 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/0105

Abstract: A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other.

Abstract translation: 复合分层芯片封装包括堆叠的第一和第二子封装。 每个子包包括主体和接线。 主体包括：具有顶表面和底表面的主要部分; 第一端子设置在主要部件的顶表面上; 以及设置在主要部分的底表面上的第二端子。 第一端子和第二端子电连接到布线。 第一子包和第二子包以不同于参考相对位置关系的特定相对位置关系彼此排列。