公开(公告)号：US20090045523A1

公开(公告)日：2009-02-19

申请号：US11889693

申请日：2007-08-15

Applicant: Wen-Jeng Fan ,  Li-Chih Fang ,  Ron Iwata

Inventor： Wen-Jeng Fan ,  Li-Chih Fang ,  Ron Iwata

IPC: H01L23/538

CPC classification number: H05K3/3436 ,  H01L23/13 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/83856 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K2201/0367 ,  H05K2201/0379 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor device primarily comprises semiconductor packages with a plurality of micro contacts and solder paste to soldering the micro contacts. Each semiconductor package comprises a substrate and a chip disposed on the substrate. The micro contacts of the bottom semiconductor package are a plurality of top bumps located on the upper surface of the substrate. The micro contacts of the top semiconductor package are a plurality of bottom bumps located on the lower surface of the substrate. The bottom bumps are aligned with the top bumps and are electrically connected each other by the solder paste. Therefore, the top bumps and the bottom bumps have the same soldering shapes and dimensions for evenly soldering to avoid breakages of the micro bumps during stacking.

Abstract translation: 叠层半导体器件主要包括具有多个微触点和焊膏以焊接微触点的半导体封装。 每个半导体封装包括衬底和设置在衬底上的芯片。 底部半导体封装的微触点是位于衬底的上表面上的多个顶部凸起。 顶部半导体封装的微触点是位于衬底的下表面上的多个底部凸起。 底部凸块与顶部凸起对准，并通过焊膏彼此电连接。 因此，顶部凸块和底部凸块具有相同的焊接形状和尺寸以便均匀焊接，以避免在堆叠期间微凸块的破损。

公开(公告)号：US20080079140A1

公开(公告)日：2008-04-03

申请号：US11868919

申请日：2007-10-08

Applicant: Peter Salmon

Inventor： Peter Salmon

IPC: H01L23/50 ,  H05K1/16

CPC classification number: H05K3/363 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05573 ,  H01L2224/11332 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/81052 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3651 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4015 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server or supercomputer embodiment is also described.

Abstract translation: 本说明书描述了用于制造电子系统模块的技术。 该模块包括具有窄至5微米或更小的迹线宽度的柔性多层互连电路。 与用于制造液晶显示器，LCD，面板的玻璃面板制造设备相似，优选地用于制造互连电路。 使用剥离层在玻璃面板上制造多层互连电路。 在互连电路上形成特殊的组装层，该电路包括在输入/输出（I / O）焊盘位置处形成有开口的厚电介质层。 使用刮刀将焊膏沉积在开口中以形成填充有焊料的孔。 IC芯片在I / O焊盘位置处设有金柱凸起，并且这些凸块插入孔中以形成倒装芯片连接。 IC芯片经过测试和返工。 相同的凹凸/连接可用于连接细间距电缆。 提供模块封装层用于密封和电磁屏蔽。 还描述了刀片服务器或超级计算机实施例。

公开(公告)号：US07266882B2

公开(公告)日：2007-09-11

申请号：US10475383

申请日：2002-04-22

Applicant: Tapani Ryhanen ,  Hans Otto Scheck ,  Ove Öhman ,  Olle Larsson ,  Mike Read ,  Tomas Lindström

Inventor： Tapani Ryhanen ,  Hans Otto Scheck ,  Ove Öhman ,  Olle Larsson ,  Mike Read ,  Tomas Lindström

IPC: H01F41/02

CPC classification number: H01S4/00 ,  H01C17/06 ,  H01F17/0033 ,  H01F27/2804 ,  H01F27/2895 ,  H01F41/04 ,  H01F41/041 ,  H01F41/08 ,  H05K1/0272 ,  H05K1/165 ,  H05K3/0014 ,  H05K3/107 ,  H05K3/205 ,  H05K3/4614 ,  H05K2201/0379 ,  H05K2201/09036 ,  H05K2201/09118 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/0594 ,  H05K2203/1105 ,  H05K2203/135 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49146 ,  Y10T29/49172 ,  Y10T29/49176 ,  Y10T29/4922

Abstract: Manufacturing of miniaturized three-dimensional electric components are presented, as well as components manufactured by the methods. The manufacturing methods comprise micro-replication of at least one master structure, e.g. via a mould structure, in at least one polymer layer onto which layer at least one conductive path is provided.

Abstract translation: 提出了小型化三维电气部件的制造以及通过这些方法制造的部件。 制造方法包括至少一个主结构的微复制，例如。 通过模具结构，在至少一个聚合物层中，至少一个导电路径被设置在该层上。

公开(公告)号：US20070137887A1

公开(公告)日：2007-06-21

申请号：US11702552

申请日：2007-02-06

Applicant: Itsuo Watanabe ,  Kenzo Takemura ,  Akira Nagai ,  Kazuhiro Isaka ,  Osamu Watanabe ,  Kazuyoshi Kojima

Inventor： Itsuo Watanabe ,  Kenzo Takemura ,  Akira Nagai ,  Kazuhiro Isaka ,  Osamu Watanabe ,  Kazuyoshi Kojima

IPC: H05K1/09 ,  B32B7/02

CPC classification number: H01L24/83 ,  C09J9/02 ,  H01L23/49883 ,  H01L24/29 ,  H01L24/90 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0271 ,  H05K3/323 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0379 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T156/10 ,  Y10T156/109 ,  Y10T428/24942 ,  Y10T428/24959 ,  Y10T428/2852 ,  Y10T428/31511 ,  Y10T428/31515 ,  Y10T428/31855 ,  H01L2924/00

Abstract: An adhesive for bonding and securing a semiconductor chip to a circuit board and electrically connecting the electrodes of the two, and containing an adhesive resin composition and an inorganic filler being contained in an amount of 10 to 200 parts by weight of 100 parts by weight of the adhesive resin composition.

Abstract translation: 一种用于将半导体芯片接合并固定到电路板并电连接两个电极的粘合剂，并且包含粘合剂树脂组合物和无机填料，其含量为10至200重量份，100重量份的100重量份 粘合剂树脂组合物。

公开(公告)号：US07205177B2

公开(公告)日：2007-04-17

申请号：US11171483

申请日：2005-06-30

Applicant: Walter De Raedt ,  Steven Brebels ,  Steven Sanders ,  Tom Torfs ,  Eric Beyne

Inventor： Walter De Raedt ,  Steven Brebels ,  Steven Sanders ,  Tom Torfs ,  Eric Beyne

IPC: H01L21/48 ,  H01L23/48 ,  B23K31/02

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3171 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27013 ,  H01L2224/2741 ,  H01L2224/29017 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83051 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/1433 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/381 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/81 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2224/45099

Abstract: A method of bonding two elements such as wafers used in microelectronics applications is disclosed. One inventive aspect relates to a method for bonding comprising producing on a first main surface of a first element a first solder ball, producing on a first main surface of a second element a second solder ball, providing contact between the first solder ball and the second solder ball, bonding the first element and the second element by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a nonconductive material, such that the upper part of the first solder ball is not covered by the non-conductive material. Devices related to such methods are also disclosed.

Abstract translation: 公开了在微电子应用中使用诸如晶片之类的两个元件的方法。 一个发明方面涉及一种用于接合的方法，包括在第一元件的第一主表面上产生第一焊球，在第二元件的第一主表面上产生第二焊球，在第一焊球和第二焊球之间提供接触 焊球，通过施加回流作用来接合第一元件和第二元件，由此焊球熔化并形成接合的焊球结构。 在接合之前，第一焊球侧向嵌入非导电材料，使得第一焊球的上部不被非导电材料覆盖。 还公开了与这些方法相关的装置。

公开(公告)号：US20070045869A1

公开(公告)日：2007-03-01

申请号：US11313435

申请日：2005-12-19

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H01L23/48

CPC classification number: H01L21/563 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13019 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/381 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/0379 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A chip package includes a chip, a carrier, and at least a bump connecting structure for connecting the chip to the carrier. The bump connecting structure includes a first metal bump disposed on a chip pad of the chip and has a first height relative to a passivation layer of the chip, a second metal bump disposed on a carrier pad of the carrier and has a second height relative to a solder mask layer of the carrier, and a middle metal part disposed between the first and the second metal bumps. The sum of the minimum distance between the first and the second metal bumps, the first height of the first metal bump, and the second height of the second metal bump is less than 60 micrometers. The melting point of the middle metal part is lower than that of the first and the second metal bumps.

Abstract translation: 芯片封装包括芯片，载体和用于将芯片连接到载体的至少一个凸块连接结构。 凸块连接结构包括设置在芯片的芯片焊盘上并具有相对于芯片的钝化层的第一高度的第一金属凸块，设置在载体的载体焊盘上的第二金属凸块，并且具有相对于 载体的焊接掩模层，以及设置在第一和第二金属凸块之间的中间金属部件。 第一和第二金属凸块之间的最小距离，第一金属凸块的第一高度和第二金属凸块的第二高度之和小于60微米。 中间金属部分的熔点低于第一和第二金属凸块的熔点。

公开(公告)号：US20060180927A1

公开(公告)日：2006-08-17

申请号：US11057696

申请日：2005-02-14

Applicant: Daisuke Takai ,  Masami Aihara ,  Koichi Takahashi

Inventor： Daisuke Takai ,  Masami Aihara ,  Koichi Takahashi

IPC: H01L23/48

CPC classification number: H05K3/4092 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/72 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L24/92 ,  H01L2224/13099 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32014 ,  H01L2224/73203 ,  H01L2224/81136 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2224/83907 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K3/326 ,  H05K7/1069 ,  H05K2201/0379 ,  H05K2201/0397 ,  H01L2924/01024 ,  H01L2924/01042 ,  H01L2924/01028 ,  H01L2924/0104 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A contact structure includes contact members having leg portions which are deflected using internal stresses. Since the internal stress is used, the leg portions of the contact members are easily and reliably deflected even when the size of the contact members is reduced in accordance with the size reduction of an electronic component. Since the leg portions are elastically deformed and function as elastic contacts, a strain caused by a difference in coefficient of thermal expansion between the electronic component and the substrate can be absorbed by the contact members. In addition, since a plurality of elastic contacts are provided, even if there is a displacement between the electronic component and the substrate, an electrical connection between the electronic component and the substrate is reliably obtained.

Abstract translation: 接触结构包括具有使用内部应力偏转的腿部的接触构件。 由于使用内部应力，即使当根据电子部件的尺寸减小而减小接触构件的尺寸时，接触构件的腿部也容易且可靠地偏转。 由于腿部弹性变形并且起到弹性接触的作用，所以由电子部件和基板之间的热膨胀系数的差异引起的应变可被接触部件吸收。 此外，由于设置了多个弹性触点，所以即使电子部件与基板之间存在位移，也可以可靠地获得电子部件与基板之间的电连接。

公开(公告)号：US07042088B2

公开(公告)日：2006-05-09

申请号：US10796253

申请日：2004-03-10

Applicant: Tony H. Ho

Inventor： Tony H. Ho

IPC: H01L23/52

CPC classification number: H05K3/3436 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/131 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/17051 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3463 ,  H05K2201/0379 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The present invention includes a semiconductor package that forms the solder array joints on the die surface and corresponding BGA substrate and PCB respectively. The life times of array solder joints are increased through the use of two sets of array joints. The top array comprises a plurality of high melting solder joints and a plurality of low melting solder joints, while the bottom array comprises a plurality of high melting solder joints only. The reflow temperature of SMT assembly is between the aforementioned high melting point and low melting point of solder joints. In addition, each solder joint comprises a flat surface at its front edge.

Abstract translation: 本发明包括分别在模具表面上形成焊料阵列接头和相应的BGA基板和PCB的半导体封装。 阵列焊点的寿命通过使用两组阵列接头而增加。 顶部阵列包括多个高熔点焊接点和多个低熔点焊接点，而底部阵列仅包括多个高熔点焊接点。 SMT组装的回流温度在上述高熔点和低熔点焊点之间。 此外，每个焊接接头在其前边缘处包括平坦表面。

公开(公告)号：US20050214971A1

公开(公告)日：2005-09-29

申请号：US10907158

申请日：2005-03-23

Applicant: Ching-Fu Hung

Inventor： Ching-Fu Hung

IPC: H01L21/44 ,  H01L21/56 ,  H01L21/60 ,  H01L23/485 ,  H05K3/34

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73203 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K3/3473 ,  H05K2201/0379 ,  H05K2201/1025 ,  H05K2203/043 ,  Y02P70/613 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A bumping process, a bump structure, a packaging process and a package structure are described. The bump structure comprises a first solder portion, a second solder portion and a conductive layer. The second solder portion is disposed on the first solder portion and the conductive layer is disposed between the first solder portion and the second solder portion. The bumping process produces a bump structure having a greater height. The bumping process can also be applied in a package process to form a package structure having a highly reliable connection between a chip and a packaging substrate.

Abstract translation: 描述了碰撞过程，凸块结构，包装过程和包装结构。 凸块结构包括第一焊料部分，第二焊料部分和导电层。 第二焊料部分设置在第一焊料部分上，并且导电层设置在第一焊料部分和第二焊接部分之间。 碰撞过程产生具有较大高度的凸块结构。 碰撞过程也可以应用于封装工艺中以形成具有在芯片和封装衬底之间的高度可靠连接的封装结构。

公开(公告)号：US06815313B2

公开(公告)日：2004-11-09

申请号：US10033397

申请日：2001-12-27

Applicant: Hiromi Yatsuda

Inventor： Hiromi Yatsuda

IPC: H01L21301

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L24/97 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/10666 ,  H05K2203/1147 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: A first substrate has a plurality of bumps and a second substrate has a plurality of openings at positions in registration with the plurality of bumps when the first and second substrates are placed one on top of the other in a confronting manner. The first and second substrates are put together by fusing a sealing wall formed on the second substrate, to hermetically seal an electronic device lying on the first substrate therein. Gas that may be generated upon fusing of the sealing wall can be effectively removed through the openings in the second substrate.

Abstract translation: 第一基板具有多个凸块，并且当第一和第二基板以相对的方式一个放置在另一个基板上时，第二基板在与多个凸块对准的位置处具有多个开口。 通过将形成在第二基板上的密封壁融合，将第一和第二基板放置在一起，将位于其上的第一基板上的电子设备密封。 可以通过第二基板中的开口有效地去除在密封壁融合时产生的气体。