公开(公告)号：US20110240351A1

公开(公告)日：2011-10-06

申请号：US13012267

申请日：2011-01-24

Applicant: Hideyuki WAKITA ,  Akihide Kawaguchi

Inventor： Hideyuki WAKITA ,  Akihide Kawaguchi

IPC: H05K1/00 ,  H05K1/11 ,  H05K3/10

CPC classification number: H05K3/4644 ,  H05K1/185 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09854

Abstract: A wiring board including a core insulation layer having a connection conductor formed in a hole of the core layer, and an interlayer insulation layer laminated on one side of the core layer. The conductor of the core layer includes plating filling the hole of the core layer. The interlayer layer has a connection conductor formed in a hole of the interlayer layer. The conductor of the interlayer layer includes plating filling the hole of the interlayer layer. The conductor of the interlayer layer is stacked on the conductor of the core insulation layer. The conductors of the core and interlayer layers have lands formed on the core and interlayer layers and including metal foils and plating on the foils. The foil of the land on the core layer has a thickness which is thicker than a thickness of the foil of the land on the interlayer layer.

Abstract translation: 一种布线板，包括具有形成在芯层的孔中的连接导体的芯绝缘层和层叠在芯层的一侧上的层间绝缘层。 芯层的导体包括填充芯层的孔的电镀。 层间层具有形成在中间层的孔中的连接导体。 中间层的导体包括填充中间层的孔的电镀。 层间层的导体层叠在芯绝缘层的导体上。 芯层和层间层的导体具有形成在芯层和层间层上并且包括金属箔和箔上的电镀的焊盘。 芯层上的焊盘的厚度比层间层上焊盘厚度厚。

公开(公告)号：US08024858B2

公开(公告)日：2011-09-27

申请号：US12351954

申请日：2009-01-12

Applicant: Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

Inventor： Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

IPC: H01K3/10

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83132 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K1/036 ,  H05K1/188 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0969 ,  H05K2201/09918 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract translation: 通过提供具有第一绝缘层，第二绝缘层和导电膜的基底基板的方法制造印刷线路板。 在基于对准标记确定的位置处将电子部件放置在第一绝缘层上。 在将电子部件封闭在第二绝缘层的开口内之后，在基于对准标记确定的位置处形成暴露电子部件的端子的通孔，该位置用于确定电子部件的位置。 通孔导体形成在通孔中，导电层形成在导电膜上并被图案化以形成连接到通孔导体的导电电路。

公开(公告)号：US08004095B2

公开(公告)日：2011-08-23

申请号：US12822080

申请日：2010-06-23

Applicant: II Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

Inventor： II Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract translation: 半导体器件具有形成在半导体晶片的有源表面上的保护层。 具有预先施加的保护层的半导体管芯从半导体晶片移动并安装在载体上。 载体上的半导体管芯和接触焊盘被封装。 载体被移除。 在预先施加的保护层和接触垫上形成第一绝缘层。 在第一绝缘层和预先施加的保护层中形成通孔以暴露半导体管芯上的互连部位。 在第一绝缘层上形成互连结构，与半导体管芯和接触焊盘上的互连部位电接触。 互连结构具有形成在第一绝缘层上的再分布层，形成在再分配层上的第二绝缘层和形成在与再分布层电接触的第二电介质上的凸块下金属化层。

公开(公告)号：US20110198723A1

公开(公告)日：2011-08-18

申请号：US13095317

申请日：2011-04-27

Applicant: Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

Inventor： Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

IPC: H01L29/92

CPC classification number: H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。

公开(公告)号：US07937830B2

公开(公告)日：2011-05-10

申请号：US12213321

申请日：2008-06-18

Applicant: Takeshi Shioga ,  Yoshikatsu Ishizuki ,  John David Baniecki ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  John David Baniecki ,  Kazuaki Kurihara

IPC: H05K3/30 ,  B29C65/00

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L21/6835 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/141 ,  H05K1/162 ,  H05K3/007 ,  H05K3/4602 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0191 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.

Abstract translation: 插入件2包括由多个树脂层26,34,42,52,56形成的基座10; 埋在基座10中的薄膜电容器12，包括下电极20，电容器电介质膜22和上电极24; 通过基底10形成并与薄膜电容器12的上部电极24电连接的第一贯通电极14b; 以及通过基底10形成并电连接到薄膜电容器12的下部电极20的第二贯通电极14a，还包括：埋入基座10中并电连接到相应的上部电极24的互连件48 多个薄膜电容器12，多个第一贯通电极14b经由布线48与所述多个薄膜电容器12的上部电极24电连接，所述多个第一贯通电极 14b通过互连48电互连。

公开(公告)号：US20110072656A1

公开(公告)日：2011-03-31

申请号：US12957431

申请日：2010-12-01

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H05K3/10

CPC classification number: H01L24/10 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/112 ,  H05K2201/0769 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/0979 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49179 ,  H01L2924/00

Abstract: A method for forming an electrical structure. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.

Abstract translation: 一种形成电结构的方法。 电结构包括互连结构和衬底。 衬底包括导电焊盘和电连接到导电焊盘的多个导线迹线。 导电焊盘电连接和机械连接到互连结构。 多条导线包括第一线迹线，第二线迹线，第三线迹线和第四线迹线。 第一线迹和第二线迹均电连接到导电垫的第一侧。 第三线迹电连接到导电垫的第二侧。 第四线迹电连接到所述第一导电焊盘的第三侧。 多个导线配置成分布电流。

公开(公告)号：US20110061921A1

公开(公告)日：2011-03-17

申请号：US12952234

申请日：2010-11-23

Applicant: Hironori TANAKA

Inventor： Hironori TANAKA

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/417 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A wiring board with built-in capacitors includes a core substrate, and a high dielectric sheet including a lower electrode layer, an upper electrode layer and a dielectric layer, the dielectric layer made of a sintered ceramic body and sandwiched between the lower electrode layer and the upper electrode layer, the lower electrode layer and/or the upper electrode layer being partitioned into multiple electrodes such that the high dielectric sheet has multiple capacitors. The lower electrode layer and/or the upper electrode layer is connected to a ground line and the other one of the lower electrode layer and the upper electrode layer is connected to a power line such that the capacitors are electrically connected in parallel.

Abstract translation: 具有内置电容器的布线板包括芯基板和包括下电极层，上电极层和电介质层的高电介质层，所述电介质层由烧结陶瓷体制成并夹在下电极层和 上电极层，下电极层和/或上电极层分隔成多个电极，使得高电介质片具有多个电容器。 下电极层和/或上电极层连接到接地线，并且下电极层和上电极层中的另一个连接到电源线，使得电容器并联电连接。

公开(公告)号：US20110061912A1

公开(公告)日：2011-03-17

申请号：US12654668

申请日：2009-12-29

Applicant: Myung Sam Kang ,  Mi Sun Hwang ,  Ok Tae Kim ,  Seon Ha Kang ,  Gil Yong Shin ,  Kil Yong Yun ,  Min Jung Cho

Inventor： Myung Sam Kang ,  Mi Sun Hwang ,  Ok Tae Kim ,  Seon Ha Kang ,  Gil Yong Shin ,  Kil Yong Yun ,  Min Jung Cho

IPC: H05K1/00 ,  H05K1/11 ,  B32B38/10 ,  B29C65/00

CPC classification number: H05K3/4611 ,  H05K3/045 ,  H05K3/4069 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2203/1461 ,  H05K2203/1536 ,  Y10T156/10

Abstract: Provided are a printed circuit board (PCB), and a manufacturing method thereof. The PCB includes a stacked structure including second and third insulation layers with a first insulation layer interposed therebetween, and a conductive via having first to fourth conductive vias. A second-layer circuit pattern and a third-layer circuit pattern are buried in the first insulation layer, a first-layer circuit pattern is formed on the second insulation layer, and a fourth-layer circuit pattern is formed on the third insulation layer. A first conductive via connects the first-layer circuit pattern and the second-layer circuit pattern, a second conductive via connects the first-layer circuit pattern and the third-layer circuit pattern, a third conductive via connects the second-layer circuit pattern and the fourth-layer circuit pattern, and a fourth conductive via connects the third-layer circuit pattern and the fourth-layer circuit pattern.

Abstract translation: 提供了一种印刷电路板（PCB）及其制造方法。 PCB包括堆叠结构，其包括其间插入有第一绝缘层的第二绝缘层和第三绝缘层，以及具有第一至第四导电通孔的导电通孔。 在第一绝缘层中埋设第二层电路图形和第三层电路图案，在第二绝缘层上形成第一层电路图案，在第三绝缘层上形成第四层电路图形。 第一导电通孔连接第一层电路图案和第二层电路图案，第二导电通孔连接第一层电路图案和第三层电路图案，第三导电通孔连接第二层电路图案和 第四层电路图案和第四导电通孔连接第三层电路图案和第四层电路图案。

公开(公告)号：US07897877B2

公开(公告)日：2011-03-01

申请号：US11438424

申请日：2006-05-23

Applicant: Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

Inventor： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01L27/12 ,  H01L28/40 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/4667 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/013

Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

Abstract translation: 电容性基板及其制造方法，其中使用第一和第二玻璃层。 第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。 然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。 形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。

公开(公告)号：US20110035938A1

公开(公告)日：2011-02-17

申请号：US12923992

申请日：2010-10-19

Applicant: Young Do Kweon ,  Sung Yi ,  Hong-Won Kim

Inventor： Young Do Kweon ,  Sung Yi ,  Hong-Won Kim

IPC: H05K3/00

CPC classification number: H05K1/162 ,  H05K3/062 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09881 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method of manufacturing a capacitor-embedded printed circuit board using a first conductive layer formed on one side of an insulation layer, the method including: forming a second conductive layer on one side of the first conductive layer; forming a second electrode by removing a portion of the second conductive layer; forming a first electrode by removing a portion of the first conductive layer in correspondence with the second electrode; and forming a dielectric layer on one side of the second electrode.

Abstract translation: 一种使用形成在绝缘层的一侧上的第一导电层制造电容器嵌入式印刷电路板的方法，所述方法包括：在所述第一导电层的一侧上形成第二导电层; 通过去除所述第二导电层的一部分来形成第二电极; 通过与所述第二电极对应地移除所述第一导电层的一部分来形成第一电极; 以及在所述第二电极的一侧上形成介电层。