公开(公告)号：US20050221680A1

公开(公告)日：2005-10-06

申请号：US11093266

申请日：2005-03-28

Applicant: Gary Yasumura ,  Joseph Fjelstad ,  Kevin Grundy ,  William Wiedemann ,  Matthew Stepovich

Inventor： Gary Yasumura ,  Joseph Fjelstad ,  Kevin Grundy ,  William Wiedemann ,  Matthew Stepovich

IPC: H01R4/58 ,  H01R12/16 ,  H01R12/24 ,  H01R13/24 ,  H01R24/00 ,  H05K3/32 ,  H05K3/40

CPC classification number: H05K3/326 ,  H01R12/714 ,  H01R12/79 ,  H01R13/2407 ,  H01R13/658 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/0979

Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.

Abstract translation: 一种电互连装置，用于在要配合的两个导电元件的端部之间建立冗余触点，产生不具有电容短截线的电互连。

公开(公告)号：US06933610B2

公开(公告)日：2005-08-23

申请号：US10370422

申请日：2003-02-19

Applicant: Para Kanagasabai Segaram ,  Joseph Fjelstad ,  Belgacem Haba

Inventor： Para Kanagasabai Segaram ,  Joseph Fjelstad ,  Belgacem Haba

IPC: H01L23/60 ,  H01L29/72

CPC classification number: H01L24/48 ,  H01L23/60 ,  H01L24/49 ,  H01L24/50 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48237 ,  H01L2224/48471 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/4554

Abstract: In a semiconductor device having a semiconductor die without an ESD circuit and a separate ESD circuit and an external lead, the external lead is first bonded to the separate ESD circuit. Thereafter, the separate ESD circuit is bonded to the semiconductor die. As a result, in the process of bonding the semiconductor die, any ESD disturbance is absorbed by the ESD circuit. In addition, a semiconductor device such as a DDR DRAM memory device, has a chip carrier with a first surface having a plurality of leads and a second surface opposite to it with an aperture between them. A semiconductor die with a mounting surface and a bonding pad faces the second surface with the bonding pad in the aperture. An ESD circuit is mounted on the mounting surface in the aperture. A first electrical connector connects one of a plurality of leads to the ESD circuit and a second electrical connector connects the ESD circuit to the bonding pad.

Abstract translation: 在具有没有ESD电路的半导体管芯和单独的ESD电路和外部引线的半导体器件中，首先将外部引线接合到单独的ESD电路。 此后，将单独的ESD电路接合到半导体管芯。 结果，在半导体管芯的接合过程中，任何ESD干扰被ESD电路吸收。 此外，诸如DDR DRAM存储器件的半导体器件具有芯片载体，其具有带有多个引线的第一表面和与其相对的第二表面，并在它们之间具有孔。 具有安装表面和接合焊盘的半导体管芯具有与孔中的焊盘相对的第二表面。 ESD电路安装在孔中的安装表面上。 第一电连接器将多个引线中的一个连接到ESD电路，并且第二电连接器将ESD电路连接到接合焊盘。

公开(公告)号：US20050155223A1

公开(公告)日：2005-07-21

申请号：US11043354

申请日：2005-01-26

Applicant: Joseph Fjelstad ,  Masud Beroz ,  John Smith ,  Belgacem Haba

Inventor： Joseph Fjelstad ,  Masud Beroz ,  John Smith ,  Belgacem Haba

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01R43/02 ,  H05K3/34

CPC classification number: H01L24/29 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/86 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49431 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/83138 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/8393 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2224/8593 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T29/49179 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: A method of making a microelectronic assembly includes juxtaposing a first element having conductive leads thereon with a second element having contacts thereon, and wire bonding the conductive leads on the first element to the contacts on the second element so that elongated bonding wires extend between the conductive leads and the contacts. After the wire bonding step, the first and second elements are moved through a preselected displacement relative to one another so as to deform the bonding wires.

Abstract translation: 制造微电子组件的方法包括：在其上具有导电引线的第一元件与其上具有触点的第二元件并置，并将第一元件上的导电引线接合到第二元件上的触点，使得细长的接合线在导电 领导和联系人。 在引线接合步骤之后，第一和第二元件相对于彼此移动通过预选位移，以使接合线变形。

公开(公告)号：US20050093127A1

公开(公告)日：2005-05-05

申请号：US10947686

申请日：2004-09-23

Applicant: Joseph Fjelstad ,  Para Segaram ,  Thomas Obenhuber ,  Inessa Obenhuber ,  Kevin Grundy

Inventor： Joseph Fjelstad ,  Para Segaram ,  Thomas Obenhuber ,  Inessa Obenhuber ,  Kevin Grundy

IPC: H01L20060101 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L24/85 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49537 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/32245

Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.

Abstract translation: 具有多个表面的IC封装，用于与互连元件互连，从IC芯片连接到位于其多于一个表面上的封装组件的I / O端子，并且与空间上分离的其它器件或组件互连。

公开(公告)号：US20050014395A1

公开(公告)日：2005-01-20

申请号：US10756924

申请日：2004-01-13

Applicant: Joseph Fjelstad ,  Para Segaram ,  Thomas Obenhuber ,  Gary Yasumura

Inventor： Joseph Fjelstad ,  Para Segaram ,  Thomas Obenhuber ,  Gary Yasumura

IPC: H01R12/16 ,  H01R12/18 ,  H05K1/14 ,  H05K3/22 ,  H05K7/14 ,  H01R12/00

CPC classification number: H05K7/1431 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/716 ,  H01R12/721 ,  H05K1/14 ,  H05K1/147 ,  H05K1/148 ,  H05K3/222 ,  H05K2201/044 ,  H05K2201/1053 ,  H05K2201/10734

Abstract: A device module may be used to carry a plurality of devices, such as memory devices or other components. The device module may include a board, a first set of contact points, and a second set of contact points. A plurality of signal paths may be provided on the board, where each signal path extends between a contact point in the first set and a contact point in the second set. Each of the plurality of signal paths has substantially an identical length and a same number of turns on the board.

Abstract translation: 设备模块可以用于承载诸如存储设备或其他组件的多个设备。 设备模块可以包括板，第一组接触点和第二组接触点。 多个信号路径可以设置在板上，其中每个信号路径在第一组中的接触点和第二组中的接触点之间延伸。 多个信号路径中的每一个在板上具有基本上相同的长度和相同的匝数。

公开(公告)号：US06821821B2

公开(公告)日：2004-11-23

申请号：US09732821

申请日：2000-12-08

Applicant: Joseph Fjelstad

Inventor： Joseph Fjelstad

IPC: H01L2148

CPC classification number: H01L21/568 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/48475 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/85051 ,  H01L2224/85444 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2224/85 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electrical resistor is made by providing a sacrificial layer and conductive pads disposed on a first surface of the sacrificial layer. An electrically resistive material is deposited over the pads and on the first surface of the sacrificial layer to form at least one unit including the resistive material and the pads. At least part of the sacrificial layer is then removed so as to expose one or more of the pads.

Abstract translation: 通过提供牺牲层和设置在牺牲层的第一表面上的导电焊盘来制造电阻器。 电阻材料沉积在焊盘之上和牺牲层的第一表面上以形成包括电阻材料和焊盘的至少一个单元。 然后去除牺牲层的至少一部分，以暴露一个或多个焊盘。

公开(公告)号：US06541867B1

公开(公告)日：2003-04-01

申请号：US09625895

申请日：2000-07-26

Applicant: Joseph Fjelstad

Inventor： Joseph Fjelstad

IPC: H01L2348

CPC classification number: H01L21/568 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/6835 ,  H01L23/49827 ,  H01L2224/05001 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H05K3/20 ,  H05K3/4046 ,  H05K2201/0133 ,  H05K2201/09118 ,  H05K2201/10378 ,  H05K2203/049 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2224/05664

Abstract: A component for mounting semiconductor chips or other microelectronic units includes a compliant, sheet-like body with arrays of sheet-like conductive pads on upper and lower surfaces of the body. Flexible leads extending through the body interconnect conductive pads on the upper and lower surfaces. The leads are desirably formed from wire, such as gold wire, that is bonded to the conductive pads using a conductive epoxy or a eutectic bonding alloy. The component is made using sacrificial base sheets having conductive terminal portions to which the leads are initially bonded. The compliant body is formed by injecting a flowable material between the base sheets, curing the material and removing the base sheets by etching. The flowable material surrounds the leads such that the leads are supported by the cured compliant layer. The component may be used as an interposer or as a test socket.

Abstract translation: 用于安装半导体芯片或其他微电子单元的部件包括柔顺的片状体，其具有在主体的上表面和下表面上的片状导电焊盘的阵列。 穿过主体的柔性引线互连上表面和下表面上的导电焊盘。 引线期望地由导线（例如金线）形成，其使用导电环氧树脂或共晶接合合金结合到导电焊盘。 该部件使用具有导电端子部分的牺牲基片制成，引线最初接合到该导电端子部分。 柔性体通过在基片之间注入可流动材料，固化材料并通过蚀刻去除基片来形成。 可流动材料围绕引线，使得引线由固化的柔性层支撑。 该组件可以用作插入器或测试插座。

公开(公告)号：US06541845B2

公开(公告)日：2003-04-01

申请号：US09777781

申请日：2001-02-06

Applicant: Masud Beroz ,  Thomas H. DiStefano ,  Anthony B. Faraci ,  Joseph Fjelstad ,  Belgacem Haba

Inventor： Masud Beroz ,  Thomas H. DiStefano ,  Anthony B. Faraci ,  Joseph Fjelstad ,  Belgacem Haba

IPC: H01L2144

CPC classification number: H05K3/4092 ,  H01L23/49811 ,  H01L23/4985 ,  H01L23/5387 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a support layer and conductive structures extending across a surface of the support layer. The conductive structures have anchors connecting them to the support layer, and releasable or unanchored portions.

Abstract translation: 用于诸如半导体芯片的微电子器件的连接部件包括支撑层和延伸穿过支撑层的表面的导电结构。 导电结构具有将它们连接到支撑层，以及可释放或未锚定部分的锚固件。

公开(公告)号：US06465878B2

公开(公告)日：2002-10-15

申请号：US09777782

申请日：2001-02-06

Applicant: Joseph Fjelstad ,  Konstantine Karavakis

Inventor： Joseph Fjelstad ,  Konstantine Karavakis

IPC: H01L23495

CPC classification number: H01L23/3114 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/498 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/72 ,  H01L24/82 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/85424 ,  H01L2924/00011 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/01004

Abstract: A microelectronic assembly includes a microelectronic element having a first surface including a central region and a peripheral region surrounding the central region, the microelectronic element including a plurality of contacts disposed in the central region. The microelectronic assembly also includes a compliant layer over the peripheral region of the first surface, the compliant layer having a bottom surface facing toward the first surface of the microelectronic element, a top surface facing upwardly away from the microelectronic element and one or more edge surfaces extending between the top and bottom surfaces. A plurality of flexible bond ribbons are disposed over the compliant layer so that the bond ribbons extend over the top surface and one or more of the edge surfaces and the bond ribbons electrically connect the contacts to conductive terminals overlying the top surface of the compliant layer.

Abstract translation: 微电子组件包括具有包括中心区域和围绕中心区域的周边区域的第一表面的微电子元件，微电子元件包括设置在中心区域中的多个触点。 微电子组件还包括在第一表面的周边区域上的柔顺层，柔顺层具有面向微电子元件的第一表面的底表面，面向上远离微电子元件的顶表面和一个或多个边缘表面 在顶部和底部表面之间延伸。 多个柔性接合带设置在柔性层上方，使得接合带在顶表面上延伸，并且一个或多个边缘表面和接合带将触头电连接到覆盖顺应层的顶表面的导电端子。

公开(公告)号：US06329607B1

公开(公告)日：2001-12-11

申请号：US08715571

申请日：1996-09-18

Applicant: Joseph Fjelstad ,  John W. Smith

Inventor： Joseph Fjelstad ,  John W. Smith

IPC: H01R909

CPC classification number: H01L24/50 ,  H01L23/3107 ,  H01L23/49572 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/3011

Abstract: A microelectronic connection component has flexible leads formed by polymeric strips with metallic conductors thereon. The metallic conductors may be very thin, desirably less than 5 microns thick, and provide good fatigue resistance. Each strip may have two conductors thereon, one serving as a principal or signal conductor for connection to a contact on a chip or other microelectronic element and the other serving as potential reference or ground conductor. The potential reference conductor on the lead provides enhanced resistance to crosstalk.

Abstract translation: 微电子连接部件具有由其上具有金属导体的聚合物条形成的柔性引线。 金属导体可以非常薄，期望小于5微米厚，并且提供良好的耐疲劳性。 每个条带可以在其上具有两个导体，一个用作主体或信号导体，用于连接到芯片或其他微电子元件上的触点，另一个用作电位参考或接地导体。 引线上的电位参考导体提供增强的串扰电阻。