公开(公告)号：US09646942B2

公开(公告)日：2017-05-09

申请号：US13403511

申请日：2012-02-23

Applicant: Jing-Cheng Lin ,  Po-Hao Tsai

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/00 ,  B23K1/00 ,  B23K101/42 ,  H01L23/498

CPC classification number: H01L24/11 ,  B23K1/0016 ,  B23K2101/42 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The mechanisms for forming bumps on packaged dies and package substrates reduce variation of bump heights across the packaged dies and packaged substrates. Bumps are designed to have different widths to counter the higher plating current near edge(s) of dies or substrates. Bump sizes can be divided into different zones depending on the bump patterns and densities across the packaged die and/or substrates. Smaller bumps near edges reduce the thickness of plated film(s), which would have been thicker due to being near the edges. As a result, the bump heights across the packaged dies and/or substrates can be kept significantly constant and chip package can be properly formed.

公开(公告)号：US08962392B2

公开(公告)日：2015-02-24

申请号：US13418868

申请日：2012-03-13

Applicant: Chin-Fu Kao ,  Jing-Cheng Lin ,  Jui-Pin Hung ,  Szu Wei Lu

Inventor： Chin-Fu Kao ,  Jing-Cheng Lin ,  Jui-Pin Hung ,  Szu Wei Lu

IPC: H01L21/50 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/568 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die.

Abstract translation: 一种方法包括将载体粘合在顶模上。 该方法还包括固化设置在基底和顶模之间的底部填充物。 该方法还包括在固化期间在载体上施加力。 该方法还包括从顶模移除载体。

公开(公告)号：US08928159B2

公开(公告)日：2015-01-06

申请号：US12874952

申请日：2010-09-02

Applicant: Hsin Chang ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

Inventor： Hsin Chang ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L21/683 ,  H01L21/768 ,  H01L23/544 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00

Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

Abstract translation: 一种器件包括衬底和包括穿透衬底的导电贯穿衬底通孔（TSV）的对准标记。

公开(公告)号：US08872326B2

公开(公告)日：2014-10-28

申请号：US13597868

申请日：2012-08-29

Applicant: Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

IPC: H01L23/48

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/27 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00011

Abstract: The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure.

Abstract translation: 上述形成半导体器件封装的机构由于相对简单的工艺流程而提供了低成本的制造工艺。 通过形成具有再分布层的互连结构以使得能够在封装结构下方的一个或多个管芯接合，整体封装的翘曲大大降低。 此外，形成互连结构，而不使用模塑料，这减少了颗粒污染。 翘曲和颗粒污染的减少会提高产量。 此外，形成的半导体器件封装具有低的形状因数，其中一个或多个管芯装配在封装结构和互连结构之间的空间的下方。

公开(公告)号：US08772945B2

公开(公告)日：2014-07-08

申请号：US13457841

申请日：2012-04-27

Applicant: Yung-Chi Lin ,  Wen-Chih Chiou ,  Yen-Hung Chen ,  Sylvia Lo ,  Jing-Cheng Lin

Inventor： Yung-Chi Lin ,  Wen-Chih Chiou ,  Yen-Hung Chen ,  Sylvia Lo ,  Jing-Cheng Lin

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05541 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05552

Abstract: A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like.

Abstract translation: 公开了一种用于向TSV提供沉积在TSV的顶表面下方的阻挡层的系统和方法，顶表面具有减小的地形变化。 将底部TSV焊盘沉积到通孔中，然后抛光，使得顶表面在衬底顶表面下方。 然后在通孔中沉积阻挡层，并且沉积在阻挡层上的顶部TSV焊盘。 顶部的TSV屏障垫被抛光，以使顶部TSV焊盘的顶部表面与衬底的高度一致。 阻挡垫可以小于约1微米厚，并且顶部TSV垫可以小于约6微米厚。 阻挡垫可以是来自顶部和底部TSV垫的不同金属，并且可以选自包括钛，钽，钴，镍等的组。

公开(公告)号：US20140061897A1

公开(公告)日：2014-03-06

申请号：US13624356

申请日：2012-09-21

Applicant: Jing-Cheng Lin ,  Po-Hao Tsai

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/498 ,  H01L21/28

CPC classification number: H01L24/11 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/06102 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11612 ,  H01L2224/11614 ,  H01L2224/1182 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/14155 ,  H01L2224/14156 ,  H01L2224/14177 ,  H01L2224/14515 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16168 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01108 ,  H01L2224/11 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/00

Abstract: A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar.

Abstract translation: 封装结构包括通过将第一基板上的金属柱连接到第二基板上的连接器而将第一基板接合到第二基板。 第一金属柱形成在第一衬底的第一区域上并覆盖并电连接到金属焊盘，第二金属柱形成在第一衬底的第二区域中的钝化层上。 在金属柱和第一连接器之间形成第一焊接区域，在第二金属柱和第二连接器之间形成第二焊点区域。 第一金属柱的厚度大于第二金属柱的厚度。

公开(公告)号：US20130270690A1

公开(公告)日：2013-10-17

申请号：US13445734

申请日：2012-04-12

Applicant: Cheng-Chieh Hsieh ,  Jing-Cheng Lin

Inventor： Cheng-Chieh Hsieh ,  Jing-Cheng Lin

IPC: H01L23/34 ,  H01L21/50

CPC classification number: H01L23/473 ,  H01L21/4882 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a first oxide layer on a surface of an integrated heat spreader, and forming a second oxide layer on top surfaces of fins, wherein the fins are parts of a heat sink. The integrated heat spreader is bonded to the heat sink through the bonding of the first oxide layer to the second oxide layer.

Abstract translation: 一种方法包括在集成散热器的表面上形成第一氧化物层，并且在翅片的顶表面上形成第二氧化物层，其中散热片是散热片的一部分。 集成散热器通过第一氧化物层与第二氧化物层的结合而结合到散热器。

公开(公告)号：US20130200529A1

公开(公告)日：2013-08-08

申请号：US13369126

申请日：2012-02-08

Applicant: Jing-Cheng Lin ,  Szu Wei Lu ,  I-Hsuan Peng

Inventor： Jing-Cheng Lin ,  Szu Wei Lu ,  I-Hsuan Peng

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/18 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/17 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1712 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00

Abstract: Semiconductor device packaging methods and structures thereof are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a plurality of second dies to a top surface of a first die, and determining a distance between each of the plurality of second dies and the first die. The method also includes determining an amount of underfill material to dispose between the first die and each of the plurality of second dies based on the determined distance, and disposing the determined amount of the underfill material under each of the plurality of second dies.

Abstract translation: 公开了半导体器件封装方法及其结构。 在一个实施例中，封装半导体器件的方法包括将多个第二管芯耦合到第一管芯的顶表面，以及确定多个第二管芯和第一管芯之间的距离。 该方法还包括基于确定的距离来确定在第一模具和第一模具中的每一个之间配置的底部填充材料的量，以及将确定量的底部填充材料设置在多个第二模具的每一个下。

公开(公告)号：US20130175694A1

公开(公告)日：2013-07-11

申请号：US13345485

申请日：2012-01-06

Applicant: Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: H01L21/58 ,  H01L23/485 ,  H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49816 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/83

Abstract: A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.

Abstract translation: 一种方法包括在衬底上形成电介质层，在电介质层上形成互连结构，以及将管芯结合到互连结构。 然后去除衬底，并对电介质层进行图案化。 连接器形成在电介质层的表面，其中连接器电耦合到管芯。

公开(公告)号：US20130154062A1

公开(公告)日：2013-06-20

申请号：US13328746

申请日：2011-12-16

Applicant: Jing-Cheng Lin ,  Ying-Da Wang ,  Li-Chung Kuo ,  Szu Wei Lu

Inventor： Jing-Cheng Lin ,  Ying-Da Wang ,  Li-Chung Kuo ,  Szu Wei Lu

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a first notch having a first width, and then forming a second notch within the first notch such that the second notch has a second width less than the first width. The second notch extends through the substrate, thereby dicing the substrate. The difference in widths between the first width and the second width results in a ledge along the sidewalls of the dice. The dice may be placed on a substrate, e.g., an interposer, and underfill placed between the dice and the substrate. The ledge prevents or reduces the distance the underfill is drawn up between adjacent dice. A molding compound may be formed over the substrate.

Abstract translation: 提供具有沿侧壁的凸缘的模具和形成模具的方法。 还提供了一种包装模具的方法。 通过形成具有第一宽度的第一凹口，然后在第一凹口内形成第二凹槽，使得第二凹槽具有小于第一宽度的第二宽度，来切割诸如经处理晶片的基底。 第二凹口延伸穿过衬底，从而切割衬底。 第一宽度和第二宽度之间的宽度差导致沿着骰子的侧壁的凸缘。 骰子可以放置在基底上，例如插入物，以及放置在骰子和基底之间的底部填充物。 凸缘防止或减少底部填充物在相邻骰子之间的距离。 可以在基材上形成模塑料。