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    STORAGE CONTROLLER AND OPERATING METHOD OF THE STORAGE CONTROLLER
    11.
    发明公开
    STORAGE CONTROLLER AND OPERATING METHOD OF THE STORAGE CONTROLLER 审中-公开

    公开(公告)号：US20240311304A1

    公开(公告)日：2024-09-19

    申请号：US18502233

    申请日：2023-11-06

    申请人： Samsung Electronics Co., Ltd.

    发明人： Minsik OH ,  Donggil KANG ,  Kyungjune CHO ,  Jongmin KIM ,  Jinwoo SONG ,  Kyungsik UM ,  Myunggwan JEONG

    IPC分类号： G06F12/0815 ,  G06F12/0862

    CPC分类号： G06F12/0815 ,  G06F12/0862

    摘要： A storage controller includes a host interface configured to communicate with a host, a buffer memory configured to buffer data read from a non-volatile memory, a cache memory including a plurality of cache lines and configured to store the data in at least one of the plurality of cache lines, and a cache controller configured to manage a status bitmap. The status bitmap indicates priority information of the plurality of cache lines according to an operation corresponding to a request received from the host interface, and the cache controller is further configured to select a victim cache line, among the plurality of cache lines, to be replaced based on the status bitmap. In this case, the operation corresponding to the request corresponds to one of normal read, prefetch, read-after-read, and read-after-prefetch.

    Techniques for pre-fetching information using pattern detection
    14.
    发明授权
    Techniques for pre-fetching information using pattern detection 有权

    公开(公告)号：US12079128B2

    公开(公告)日：2024-09-03

    申请号：US17723096

    申请日：2022-04-18

    申请人： Micron Technology, Inc.

    发明人： Vanaja Urrinkala ,  Niraimathi N S

    IPC分类号： G06F12/0862

    CPC分类号： G06F12/0862 ,  G06F2212/6022

    摘要： Methods, systems, and devices supporting techniques for pre-fetching information using pattern detection are described. Some memory systems may support pre-fetching information, such as logical-to-physical (L2P) mapping tables, data, or both, if a sequential pattern of read commands is detected. In some examples, the memory system may store a list of logical addresses indicated by received read commands and may determine whether the list corresponds to a sequential pattern independent of intervening write-alike commands. The list may store previous logical addresses for read commands, allowing the memory system to determine whether subsequent read commands form a sequential pattern. Additionally or alternatively, the memory system may track a ratio of hibernate commands to other commands (e.g., sequential read commands) and may refrain from pre-fetching L2P mapping tables for a detected sequence if the tracked ratio satisfies (e.g., exceeds) a threshold ratio.

    MULTI-PORT QUEUEING CACHE AND DATA PROCESSING SYSTEM INCLUDING THE SAME
    16.
    发明公开
    MULTI-PORT QUEUEING CACHE AND DATA PROCESSING SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240289278A1

    公开(公告)日：2024-08-29

    申请号：US18654803

    申请日：2024-05-03

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Heonsoo LEE ,  Byungchul Hong ,  Junseok Park ,  Jaehun Chung

    IPC分类号： G06F12/0862 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06

    CPC分类号： G06F12/0862 ,  G06F9/3816 ,  G06F12/0261 ,  G06F12/0646

    摘要： In some embodiments, a multi-port queueing cache includes a plurality of first ports, a plurality of second ports, a plurality of request handlers respectively coupled to the plurality of first ports, a cache storage unit coupled to the plurality of second ports, a reserve interface configured to exchange at least one address and at least one reserved cache line number, and a request interface configured to exchange the at least one reserved cache line number and at least one data. The reserve interface and the request interface are disposed between the plurality of request handlers and the cache storage unit. The cache storage unit includes a plurality of cache lines configured to store the plurality of data. The cache storage unit is configured to output a portion of the plurality of addresses, and receive a portion of the plurality of data corresponding to the portion of the plurality of addresses.