公开(公告)号：US07833882B2

公开(公告)日：2010-11-16

申请号：US11651534

申请日：2007-01-10

Applicant: Yukihiro Tsuji ,  Toshio Nomaguchi

Inventor： Yukihiro Tsuji ,  Toshio Nomaguchi

IPC: H01L21/322 ,  H01L21/469 ,  H01L21/00

CPC classification number: H01S5/0425 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48666 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/0101 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01088 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01S5/2214 ,  H01S5/227 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of producing a semiconductor device, including: a first plasma processing step of processing a surface of a resin layer laid on a semiconductor element and containing silicon, with a first plasma generated from a gas containing oxygen and fluorine, thereby forming an oxide film; and an electrode pad forming step of forming an electrode pad of a metal on the oxide film.

Abstract translation: 一种制造半导体器件的方法，包括：第一等离子体处理步骤，其处理由半导体元件上放置的含有硅的树脂层的表面，并由含有氧和氟的气体产生的第一等离子体形成氧化膜 ; 以及在所述氧化物膜上形成金属的电极焊盘的电极焊盘形成工序。

公开(公告)号：US07807502B2

公开(公告)日：2010-10-05

申请号：US12762438

申请日：2010-04-19

Applicant: Chua Swee Kwang ,  Chia Yong Poo

Inventor： Chua Swee Kwang ,  Chia Yong Poo

IPC: H01L21/00

CPC classification number: H01L24/32 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die includes a recess, and the discrete component is contained in the recess encapsulated in the die attach polymer. A method for fabricating the package includes the steps of: attaching the discrete component to the substrate, placing the die attach polymer on the discrete component and the substrate, pressing the die into the die attach polymer to encapsulate the discrete component in the recess and attach the die to the substrate, and then placing the die in electrical communication with the discrete component. An electronic system includes the semiconductor package mounted to a system substrate.

Abstract translation: 半导体封装包括具有触点的基板和与触点电连通的基板上的分立元件。 封装还包括与触点电连通的衬底上的半导体管芯，以及将管芯附接到衬底的管芯附接聚合物。 模具包括凹部，并且分离的部件包含在封装在管芯附着聚合物中的凹部中。 一种用于制造封装的方法包括以下步骤：将分立组件附接到衬底，将裸片附着聚合物放置在分立组件和衬底上，将模具压入芯片附着聚合物以将分立组件封装在凹槽中并附着 将裸片冲压到基板上，然后将模具放置在与分立元件电连通的位置。 电子系统包括安装到系统基板的半导体封装。

公开(公告)号：US20100244282A1

公开(公告)日：2010-09-30

申请号：US12813472

申请日：2010-06-10

Applicant: Kia Silverbrook ,  Laval Chung-Long-Shan ,  Kiangkai Tankongchumruskul

Inventor： Kia Silverbrook ,  Laval Chung-Long-Shan ,  Kiangkai Tankongchumruskul

IPC: H01L23/49 ,  H01L23/498

CPC classification number: H01L24/85 ,  H01L21/56 ,  H01L23/3157 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48699 ,  H01L2224/4899 ,  H01L2224/78313 ,  H01L2224/85181 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/859 ,  H01L2224/8592 ,  H01L2224/8593 ,  H01L2224/85947 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An electronic component assembly that has a supporting structure, an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors, the integrated circuit die and the PCB being mounted to the supporting structure by a die attach film such that they are adjacent and spaced from each other and, wire bonds electrically connecting the contact pads to the conductors. An intermediate portion of each of the wire bonds is adhered to the die attach film to lower the profile of the wire bond arcs.

Abstract translation: 具有支撑结构的电子部件组件，具有多个接触焊盘的集成电路芯片，具有多个导体的印刷电路板，所述集成电路管芯和所述PCB通过管芯附着膜安装到所述支撑结构， 它们彼此相邻并且彼此分开，并且引线将电接触焊盘电连接到导体。 每个线接合的中间部分粘附到管芯附着膜上以降低引线接合弧的轮廓。

公开(公告)号：US07777353B2

公开(公告)日：2010-08-17

申请号：US11838396

申请日：2007-08-14

Applicant: Shinya Ohkawa

Inventor： Shinya Ohkawa

IPC: H01L23/48

CPC classification number: H01L24/85 ,  H01L21/4842 ,  H01L23/4952 ,  H01L23/49551 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48483 ,  H01L2224/4899 ,  H01L2224/49052 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: In a semiconductor device, first wires each having a relatively low loop height are formed between a first lead and a plurality of first electrode pads aligned in a first line, and then second wires each having a relatively high loop height are formed between a second lead and a plurality of second electrode pads aligned in a second line, wherein the second line is distanced from the first line in view of the first and second leads. Wire bonding is sequentially performed so as to increase the height difference between the first wire and the second wire, thus avoiding the occurrence of electric short-circuiting between adjacently arranged wires. In wire bonding, a bump forming process, a ball bonding process, and a wedge bonding process are sequentially performed. It is preferable that the second lead be vertically distanced from the first lead in the thickness direction.

Abstract translation: 在半导体器件中，在第一引线和与第一线对准的多个第一电极焊盘之间形成各自具有较低环路高度的第一布线，然后在第二引线 以及在第二线中排列的多个第二电极焊盘，其中从第一和第二引线的角度来看，第二线与第一线分开。 依次进行引线接合，以增加第一线和第二线之间的高度差，从而避免相邻布置的线之间发生电短路。 在引线接合中，依次进行凸块形成工艺，球接合工艺和楔形粘结工艺。 优选地，第二引线在厚度方向上与第一引线垂直地间隔开。

公开(公告)号：US20100203677A1

公开(公告)日：2010-08-12

申请号：US12762438

申请日：2010-04-19

Applicant: Chua Swee Kwang ,  Chia Yong Poo

Inventor： Chua Swee Kwang ,  Chia Yong Poo

IPC: H01L21/98 ,  H01L21/56

CPC classification number: H01L24/32 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die includes a recess, and the discrete component is contained in the recess encapsulated in the die attach polymer. A method for fabricating the package includes the steps of: attaching the discrete component to the substrate, placing the die attach polymer on the discrete component and the substrate, pressing the die into the die attach polymer to encapsulate the discrete component in the recess and attach the die to the substrate, and then placing the die in electrical communication with the discrete component. An electronic system includes the semiconductor package mounted to a system substrate.

Abstract translation: 半导体封装包括具有触点的基板和与触点电连通的基板上的分立元件。 封装还包括与触点电连通的衬底上的半导体管芯，以及将管芯附接到衬底的管芯附接聚合物。 模具包括凹部，并且分离的部件包含在封装在管芯附着聚合物中的凹部中。 一种用于制造封装的方法包括以下步骤：将分立组件附接到衬底，将裸片附着聚合物放置在分立组件和衬底上，将模具压入芯片附着聚合物以将分立组件封装在凹槽中并附着 将裸片冲压到基板上，然后将模具放置在与分立元件电连通的位置。 电子系统包括安装到系统基板的半导体封装。

公开(公告)号：US20100093154A1

公开(公告)日：2010-04-15

申请号：US12529070

申请日：2008-01-28

Applicant: Yasuhiro Amano ,  Sadahito Misumi ,  Takeshi Matsumura

Inventor： Yasuhiro Amano ,  Sadahito Misumi ,  Takeshi Matsumura

IPC: H01L21/301 ,  B32B7/10 ,  H01L21/52 ,  H01L21/683

CPC classification number: H01L23/3121 ,  C08G18/4045 ,  C08G18/6254 ,  C08L33/08 ,  C09J175/04 ,  H01L21/6836 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/27436 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29316 ,  H01L2224/29318 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29371 ,  H01L2224/29386 ,  H01L2224/29393 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/8388 ,  H01L2224/83885 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10T428/24355 ,  H01L2924/00014 ,  H01L2924/0635 ,  H01L2924/066 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2924/05432 ,  H01L2924/0532 ,  H01L2924/04642 ,  H01L2924/05042 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: A dicing die-bonding film in which the adhesive properties during the dicing step and the peeling properties during the pickup step are controlled so that both become good, and a production method thereof, are provided. The dicing die-bonding film in the present invention is a dicing die-bonding film having a pressure-sensitive adhesive layer on a base material and a die bond layer on the pressure-sensitive adhesive layer, in which the arithmetic mean roughness X (μm) on the pressure-sensitive adhesive layer side in the die bond layer is 0.015 μm to 1 μm, the arithmetic mean roughness Y (μm) on the die bond layer side in the pressure-sensitive adhesive layer is 0.03 μm to 1 μm, and the absolute value of the difference of the X and Y is 0.015 or more.

Abstract translation: 控制在切割步骤期间的粘合性能和拾取步骤期间的剥离性能使其都变得良好的切割芯片接合薄膜及其制备方法。 本发明的切割/芯片接合薄膜是在基材上具有压敏粘合剂层和压敏粘合剂层上的芯片接合层的切割芯片接合薄膜，其中算术平均粗糙度X（μm ）为0.015μm〜1μm，压敏粘合剂层的芯片接合层侧的算术平均粗糙度Y（μm）为0.03μm〜1μm， X和Y的差的绝对值为0.015以上。

公开(公告)号：US07659612B2

公开(公告)日：2010-02-09

申请号：US11409638

申请日：2006-04-24

Applicant: David R. Hembree ,  Alan G. Wood

Inventor： David R. Hembree ,  Alan G. Wood

IPC: H01L23/04

CPC classification number: H01L24/16 ,  G01R1/06716 ,  G01R1/07307 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02125 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/0333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/45116 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45655 ,  H01L2224/45684 ,  H01L2224/45698 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48455 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/4899 ,  H01L2224/48992 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/10155 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45164 ,  H01L2924/013 ,  H01L2924/00013

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Abstract translation: 半导体部件包括具有衬底接触的半导体衬底和附着到衬底触点的通线互连（TWI）。 通线互连提供了在半导体衬底的相对的第一和第二侧上具有触点的多电平互连。 通线互连（TWI）包括穿过基板触点和基板的通孔，通孔中的导线与基板接触具有接合连接，接近第一侧的导线上的第一触点和第二触点 电线靠近第二侧。 通线互连（TWI）还包括聚合物层，其部分地封装通孔互连（TWI），同时使第一触点暴露。 半导体部件可用于制造堆叠系统，模块系统和测试系统。 制造半导体部件的方法可以包括用于形成聚合物层的膜辅助成型工艺。

公开(公告)号：US20090325344A1

公开(公告)日：2009-12-31

申请号：US12165340

申请日：2008-06-30

Applicant: Hem Takiar ,  Shrikar Bhagath

Inventor： Hem Takiar ,  Shrikar Bhagath

IPC: H01L21/60

CPC classification number: H01L24/85 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/01047 ,  H01L2224/85186 ,  H01L2924/0665 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00015

Abstract: A method of fabricating a low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes.

Abstract translation: 公开了一种制造低轮廓半导体封装件的方法，该方法至少包括安装到衬底上的第一和第二层叠半导体管芯。 第一和/或第二半导体管芯可以被制造成多个再分布焊盘，其形成在多个接合焊盘上并电耦合到多个接合焊盘。 在半导体管芯从晶片形成和切割之后，可以使用根据本发明的低剖面反向引线接合将管芯安装到衬底上。 特别地，在传统的反向接合工艺中，可以在导线和再分布垫之间形成楔形键，而不必在芯片接合焊盘上使用第二线接合球。

公开(公告)号：US07622332B2

公开(公告)日：2009-11-24

申请号：US11197944

申请日：2005-08-04

Applicant: Shafidul Islam ,  Romarico Santos San Antonio

Inventor： Shafidul Islam ,  Romarico Santos San Antonio

IPC: H01L21/00 ,  H01R43/00

CPC classification number: H01L21/56 ,  H01L21/4832 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/30105 ,  H01L2924/351 ,  Y10T29/49121 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is encapsulated. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.

Abstract translation: 制造引线框架的方法和具有近芯片尺寸封装（CSP）引线计数的部分图案化引线框架封装的方法是通过用形成为网状结构的部分图案化的金属条执行制造工艺步骤的主要部分来实现的， 在一侧具有类似的引线框架，使得在另一侧上固体和平坦的网状引线框架也是刚性机械和坚固的热，以在芯片附着和引线键合过程中在没有变形或变形的情况下进行，两者在 芯片级和封装级别。 金属引线框架的底侧被图案化以便仅在封装了包括芯片和电线的前侧之后才能隔离芯片焊盘和引线接合触点。 所得的封装被电隔离使得能够进行条带测试和可靠的分割，而不必切入任何额外的金属。

公开(公告)号：US20090267214A1

公开(公告)日：2009-10-29

申请号：US12066534

申请日：2006-10-19

Applicant: Kentaro Kumazawa ,  Shigeru Kondou ,  Hidenobu Nishikawa

Inventor： Kentaro Kumazawa ,  Shigeru Kondou ,  Hidenobu Nishikawa

IPC: H01L25/065 ,  H01L23/52 ,  H01L21/56 ,  H01L23/12 ,  H01L25/07

CPC classification number: H01L24/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/32145 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40137 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/85201 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The electronic circuit device of the present invention includes at least one semiconductor element, a plurality of external connection terminals, a connecting conductor for electrically connecting semiconductor element and external connection terminals, and an insulating resin for covering the semiconductor element and supporting the connecting conductor integrally, in which the semiconductor element is buried in the insulating resin, and the terminal surface of the external connection terminals is exposed from the insulating resin.

Abstract translation: 本发明的电子电路装置包括至少一个半导体元件，多个外部连接端子，用于电连接半导体元件和外部连接端子的连接导体，以及用于覆盖半导体元件并将连接导体一体地支撑的绝缘树脂 其中半导体元件埋在绝缘树脂中，并且外部连接端子的端子表面从绝缘树脂露出。