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    SUBSTRATES AND METHODS OF MANUFACTURE
    34.
    发明申请
    SUBSTRATES AND METHODS OF MANUFACTURE 有权
    基板和制造方法

    公开(公告)号：US20160126174A1

    公开(公告)日：2016-05-05

    申请号：US14533728

    申请日：2014-11-05

    Applicant: Invensas Corporation

    Inventor： Hong Shen ,  Liang Wang ,  Gabriel Z. Guevara ,  Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

    IPC: H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

    CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

    Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

    Abstract translation: 插入器（110）在顶部和/或底部表面处具有用于连接到电路模块（例如IC 112）的接触焊盘。 插入器包括由多层（110.i）制成的衬底。 每个层可以是具有电路的衬底（110S），可能是陶瓷衬底。 基板垂直延伸。 在由对应于插入层的垂直层（310.i）制成的单个结构（310）中制造多个插入件。 沿着水平面（314）切割结构以提供插入件。 在切割之前和所有基板彼此附接之前，可以在基板表面上形成插入件的垂直导线（类似于贯穿基板通孔）。 因此，不需要对垂直导线进行贯通基板孔。 在基板彼此附接之前，也可以在基板表面上形成非垂直特征。 还提供了其他实施例。

    Symbiotic Network On Layers
    37.
    发明申请
    Symbiotic Network On Layers 有权

    公开(公告)号：US20220150184A1

    公开(公告)日：2022-05-12

    申请号：US17583872

    申请日：2022-01-25

    Applicant: Invensas Corporation

    Inventor： Javier A. DeLaCruz ,  Belgacem Haba ,  Rajesh Katkar

    IPC: H04L49/109

    Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

    Apparatus For Non-Volatile Random Access Memory Stacks
    38.
    发明申请
    Apparatus For Non-Volatile Random Access Memory Stacks 有权

    公开(公告)号：US20210193624A1

    公开(公告)日：2021-06-24

    申请号：US17122149

    申请日：2020-12-15

    Applicant: Invensas Corporation

    Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Rajesh Katkar ,  Pearl Po-Yee Cheng

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.

    Tall and fine pitch interconnects
    39.
    发明授权
    Tall and fine pitch interconnects 有权

    公开(公告)号：US10818629B2

    公开(公告)日：2020-10-27

    申请号：US16127696

    申请日：2018-09-11

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

    IPC: H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L25/065 ,  H05K3/34

    Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

    Multi-chip modules formed using wafer-level processing of a reconstituted wafer
    40.
    发明授权
    Multi-chip modules formed using wafer-level processing of a reconstituted wafer 有权

    公开(公告)号：US10546834B2

    公开(公告)日：2020-01-28

    申请号：US16246863

    申请日：2019-01-14

    Applicant: Invensas Corporation

    Inventor： Liang Wang ,  Rajesh Katkar

    IPC: H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

    Abstract: Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.

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