公开(公告)号：US20170077052A1

公开(公告)日：2017-03-16

申请号：US14853807

申请日：2015-09-14

申请人： Micron Technology, Inc.

发明人： Giorgio Mariottini ,  Sameer Vadhavkar ,  Wayne Huang ,  Anilkumar Chandolu ,  Mark Bossler

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/02135 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0361 ,  H01L2224/03906 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05082 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/05687 ,  H01L2224/10145 ,  H01L2224/114 ,  H01L2224/11472 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/3651 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/053

摘要： The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

摘要翻译： 本技术涉及制造用于管芯到管芯和/或封装到封装互连及相关系统的凸块下金属（UBM）结构的套圈。 半导体管芯包括具有固态部件的半导体材料和至少部分延伸穿过半导体材料的互连。 在半导体材料之上形成凸块下金属（UBM）结构，并且电耦合到相应的互连。 套环围绕UBM结构的侧表面的至少一部分，并且焊料材料设置在UBM结构的顶表面上。

公开(公告)号：US09583425B2

公开(公告)日：2017-02-28

申请号：US13929978

申请日：2013-06-28

申请人： Maxim Integrated Products, Inc.

发明人： Yong Li Xu ,  Tiao Zhou ,  Xiansong Chen ,  Kaysar M. Rahim ,  Viren Khandekar ,  Yi-Sheng Anthony Sun ,  Arkadii V. Samoilov

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC分类号： H01L23/49811 ,  H01L21/76885 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02165 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05563 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/10125 ,  H01L2224/13013 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26125 ,  H01L2224/29013 ,  H01L2224/32227 ,  H01L2224/3303 ,  H01L2224/33051 ,  H01L2224/3316 ,  H01L2224/81192 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83365 ,  H01L2224/83815 ,  H01L2924/351 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

摘要： A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

摘要翻译： 晶片级封装包括晶片，用于将晶片连接到电路的晶片设置的引线和设置在引线上的芯。 在一些实施例中，设置晶片的引线是铜柱，并且芯被镀在铜柱上。 在一些实施方案中，芯是聚合物丝网电镀到引线上。 在一些实施例中，芯从引线延伸至少约35微米（35微米）和50微米（50μm）。 在一些实施例中，芯覆盖在铅的表面积的至少约三分之一（1/3）和一半（1/2）之间。 在一些实施例中，芯包括从引线延伸的螺柱形状。 在一些实施例中，芯垂直延伸穿过导线。 在一些实施例中，芯沿着引线纵向延伸。 此外，芯的一部分可以从纵向芯垂直延伸。

公开(公告)号：US20160307863A1

公开(公告)日：2016-10-20

申请号：US15189369

申请日：2016-06-22

申请人： MediaTek Inc.

发明人： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Tai-Yu Chen

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/02125 ,  H01L2224/02165 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/13006 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2224/16238 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/18161 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/05552

摘要： The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

摘要翻译： 本发明提供一种半导体封装。 半导体封装包括具有中心区域和围绕中心区域的周边区域的半导体管芯。 第一导电凸块设置在中心区域的半导体管芯上。 第二导电凸块设置在周边区域的半导体管芯上。 从顶视图看，第一导电凸块与第二导电凸块的面积比大于1，小于或等于3。

公开(公告)号：US20160307859A1

公开(公告)日：2016-10-20

申请号：US15193117

申请日：2016-06-27

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chung-Hsin Lin ,  Ping-Heng Wu ,  Chao-Wen Lay ,  Hung-Mo Wu ,  Ying-Cheng Chuang

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/525 ,  H01L23/562 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

摘要翻译： 本发明提供一种半导体器件，其包括衬底，电介质层，虚拟焊盘，焊盘，再分配层和金属互连。 衬底包括非器件区域和器件区域。 介电层位于非器件区域和器件区域上。 虚拟焊盘位于非器件区的介质层上。 金属互连在非器件区的介质层中并连接到虚拟焊盘。 焊盘位于器件区域的介电层上。 缓冲层位于接合焊盘和电介质层之间。 缓冲层包括金属，金属氮化物或其组合。 再分布层在电介质层上并连接虚拟焊盘和焊盘。

公开(公告)号：US20150179565A1

公开(公告)日：2015-06-25

申请号：US14637456

申请日：2015-03-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Chih WANG ,  Yao-Hsiang LIANG

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L27/088

CPC分类号： H01L24/05 ,  H01L21/76841 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/13 ,  H01L27/088 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/13091 ,  H01L2924/206 ,  H01L2924/30201 ,  H01L2924/00 ,  H01L2924/00014

摘要： A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.

摘要翻译： 提供了用于接合半导体器件的连接结构及其形成方法。 键合结构包括铝垫结构，即厚的含铝连接垫，以及至少包含预金属层和阻挡层的含铝垫下面的底层结构。 预金属层是致密材料层，并且包括大于阻挡层的密度，并且是低表面粗糙度膜。 高密度预金属层防止等离子体损伤在下面的介电材料中产生电荷或破坏下面的半导体器件。

公开(公告)号：US20140252623A1

公开(公告)日：2014-09-11

申请号：US13792744

申请日：2013-03-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Chih WANG ,  Yao-Hsiang LIANG

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L24/05 ,  H01L21/76841 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/13 ,  H01L27/088 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/13091 ,  H01L2924/206 ,  H01L2924/30201 ,  H01L2924/00 ,  H01L2924/00014

摘要： A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.

摘要翻译： 提供了用于接合半导体器件的连接结构及其形成方法。 键合结构包括铝垫结构，即厚的含铝连接垫，以及至少包含预金属层和阻挡层的含铝垫下面的底层结构。 预金属层是致密材料层，并且包括大于阻挡层的密度，并且是低表面粗糙度膜。 高密度预金属层防止等离子体损伤在下面的介电材料中产生电荷或破坏下面的半导体器件。

公开(公告)号：US20130234251A1

公开(公告)日：2013-09-12

申请号：US13777951

申请日：2013-02-26

申请人： LAPIS SEMICONDUCTOR CO., LTD.

发明人： Chikashi FUCHIGAMI

IPC分类号： H01L27/02 ,  H01L29/78

CPC分类号： H01L27/027 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L29/78 ,  H01L2224/0215 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05078 ,  H01L2224/05124 ,  H01L2224/05187 ,  H01L2224/05551 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/10122 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/049 ,  H01L2924/07025 ,  H01L2924/05442

摘要： A semiconductor integrated device in which electrostatic discharge damage can be reliably prevented, includes a semiconductor substrate in which an electrostatic protection circuit including a second diffusion region surrounding a first diffusion region as a local region is formed in a main surface; a metal pad opposed to the main surface; and a conductive bump formed so as to face a top surface of the metal pad, wherein in a surface opposed to the metal pad of the conductive bump, a projection which is in contact with the metal pad is provided in a range opposed to the first diffusion region.

摘要翻译： 可以可靠地防止静电放电损坏的半导体集成器件包括：半导体衬底，其中在主表面上形成有包围作为局部区域的第一扩散区域的第二扩散区域的静电保护电路; 与主表面相对的金属垫; 以及形成为面对所述金属焊盘的顶面的导电性凸块，在与所述导电凸块的所述金属焊盘相对的表面中，与所述金属焊盘接触的突起设置在与所述第一 扩散区。

公开(公告)号：US08390107B2

公开(公告)日：2013-03-05

申请号：US11863290

申请日：2007-09-28

申请人： Thorsten Meyer

发明人： Thorsten Meyer

IPC分类号： H01L23/06

CPC分类号： H01L23/562 ,  H01L21/54 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02175 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/02351 ,  H01L2224/02371 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/12105 ,  H01L2224/1302 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/141 ,  H01L2224/24227 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3512 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05099

摘要： This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements.

摘要翻译： 本申请涉及包括半导体芯片，覆盖半导体芯片的成型体的半导体器件，其中模制体包括模制结构元件阵列，以及与模制结构元件接合的第一焊料元件。

公开(公告)号：US07982311B2

公开(公告)日：2011-07-19

申请号：US12317227

申请日：2008-12-19

申请人： Kevin J. Lee

发明人： Kevin J. Lee

IPC分类号： H01L23/488

CPC分类号： H01L23/49816 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02166 ,  H01L2224/02175 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16112 ,  H01L2224/17 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/3841 ,  H01L2224/29099 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/0665

摘要： An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

摘要翻译： 一种装置包括具有器件层，多个金属化层，钝化层和形成在钝化层上的金属凸块的半导体衬底，其电耦合至至少一个金属化层。 该装置还包括形成在钝化层上的焊料限制层，其掩盖金属凸块的顶表面的外边缘，从而使顶表面的外边缘不能被焊料材料润湿。

公开(公告)号：US12080636B2

公开(公告)日：2024-09-03

申请号：US17310851

申请日：2019-12-09

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： Koichi Igarashi

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L27/146

CPC分类号： H01L23/49816 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L27/14618 ,  H01L2224/0219 ,  H01L2224/03019 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/16225

摘要： In a semiconductor package in which a semiconductor substrate is mounted, thermal resistance of the semiconductor substrate is reduced. The semiconductor package includes a semiconductor substrate, an insulating layer, a metal layer, an interposer substrate, a mounting substrate, a signal transmission solder ball, and a solder member. A pad is provided on one surface of the semiconductor substrate. A different surface of the semiconductor substrate is covered with the insulating layer. The metal layer covers the insulating layer. A wire to be connected to the pad is formed on the interposer substrate. The signal transmission solder ball is jointed to the wire and the mounting substrate, and transmits a predetermined electrical signal. The solder member is jointed to the metal layer and the mounting substrate.