公开(公告)号：US09287143B2

公开(公告)日：2016-03-15

申请号：US13939966

申请日：2013-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/03823 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05548 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/10126 ,  H01L2224/11464 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/3205 ,  H01L2224/32225 ,  H01L2224/33135 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/831 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method and apparatus for a reinforced package are provided. A package component may be electrically coupled to a device through a plurality of electrical connections. A molding underfill may be interposed between the package component and the device and may encapsulate the plurality of electrical connections or a subset of the plurality of electrical connections between the package component and the device. The package component may also include a molding compound. The plurality of the electrical connections may extend through the molding compound with the molding underfill interposed between the molding compound and the device to encapsulate the plurality of electrical connections or a subset of the plurality of electrical connections between the package component and the device. The molding underfill may extend up one or more sides of the package component.

Abstract translation: 提供了一种用于增强包装的方法和装置。 封装部件可以通过多个电连接件电耦合到器件。 模制底部填充物可以插入在包装部件和装置之间，并且可以将多个电连接或多个电连接的子集封装在包装部件和装置之间。 包装组分还可以包括模塑料。 多个电连接可以延伸穿过模制化合物，其中模制底部填充物介于模制化合物和装置之间，以封装多个电连接或封装部件与装置之间的多个电连接的子集。 成型底部填充物可以向包装部件的一侧或多侧延伸。

公开(公告)号：US20160056117A1

公开(公告)日：2016-02-25

申请号：US14932530

申请日：2015-11-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Shi Liu ,  Chia-Wei Tu ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Yu-Peng Tsai

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/566 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13193 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound.

Abstract translation: 一种方法包括在金属焊盘上形成钝化层，其中金属焊盘进一步覆盖晶片的半导体衬底。 后钝化互连（PPI）被形成为电耦合到金属焊盘，其中PPI的一部分覆盖钝化层。 在PPI上形成电耦合的金属凸块。 该方法还包括在金属凸块和PPI上施加模塑料，在模塑料上施加隔离膜，将隔离膜压靠在模塑料上，以及当剥离膜压靠模塑料时固化模塑料。 然后将脱模膜从模塑料中除去。 使用刀片将晶片锯成模具，刀片通过模塑料切割。

公开(公告)号：US09269682B2

公开(公告)日：2016-02-23

申请号：US13778969

申请日：2013-02-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0348 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05109 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of forming a bump structure includes forming a metallization layer on a top metal layer by electroless plating process, forming a polymer layer over the metallization layer; forming an opening on the polymer layer to expose the metallization layer, and forming a solder bump over the exposed metallization layer to make electrical contact with the top metal layer.

Abstract translation: 形成凸块结构的方法包括通过化学镀方法在顶部金属层上形成金属化层，在金属化层上形成聚合物层; 在所述聚合物层上形成开口以暴露所述金属化层，以及在所述暴露的金属化层上形成焊料凸块以与所述顶部金属层电接触。

公开(公告)号：US20160020186A1

公开(公告)日：2016-01-21

申请号：US14863942

申请日：2015-09-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Feng CHEN ,  Chun-Hung LIN ,  Han-Ping PU ,  Chih-Hang TUNG ,  Kai-Chiang WU ,  Ming-Che HO

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/488 ,  H01L24/02 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05111 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10125 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13076 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device includes an under-bump metallization (UBM) layer over a substrate. The semiconductor device also includes a copper-containing layer having a base portion over the UBM layer. The semiconductor device further includes a solder bump over the UBM layer and over the copper-containing layer. The base portion is embedded in the solder bump. The copper-containing layer has a cylindrical shape and includes at least two segments separated by at least two openings. A first total area (A) of the at least two openings is greater than about 3% of a second total area (B) of the at least two segments. The first total area (A) is less than about 70% of the second total area (B) of the at least two segments.

Abstract translation: 半导体器件包括在衬底上的凸起下金属化（UBM）层。 半导体器件还包括在UBM层上具有基底部分的含铜层。 半导体器件还包括在UBM层上方并且在含铜层上方的焊料凸块。 基部嵌入焊料凸块中。 含铜层具有圆筒形状，并且包括至少两个由至少两个开口分开的段。 所述至少两个开口的第一总面积（A）大于所述至少两个区段的第二总面积（B）的约3％。 第一总面积（A）小于至少两段的第二总面积（B）的约70％。

公开(公告)号：US09240384B2

公开(公告)日：2016-01-19

申请号：US13621804

申请日：2012-09-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Qing Zhang ,  Haijing Cao

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/11009 ,  H01L2224/11019 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/05552

Abstract: A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

Abstract translation: 半导体器件具有形成在衬底上的第一导电层。 第一绝缘层形成在衬底和第一导电层上。 在第一导电层和第一绝缘层上形成第二导电层。 在第一绝缘层和第二导电层上形成第二绝缘层。 第二绝缘层在第二绝缘材料的表面和第二导电层的表面之间具有侧壁。 在第二绝缘层和第二导电层的表面上形成保护层。 保护层遵循第二绝缘层和第二导电层的表面和侧壁的轮廓。 在第二导电层的表面上形成凸块，并且与第二绝缘层相邻的部分形成保护层。 保护层保护第二绝缘层。

公开(公告)号：US09236365B2

公开(公告)日：2016-01-12

申请号：US14275678

申请日：2014-05-12

Applicant: Invensas Corporation

Inventor： Paul W. Sanders ,  Robert E. Jones ,  Michael F. Petras ,  Chandrasekaram Ramiah

IPC: H01L21/00 ,  H01L25/065 ,  H01L21/683 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L49/02 ,  H01L23/538 ,  H01L23/58 ,  H01L27/06

CPC classification number: H01L25/162 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/58 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0296 ,  H01L27/0629 ,  H01L28/00 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/1147 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16503 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2224/13099

Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Abstract translation: 使用集成无源器件（IPD）形成3-D IC的方法包括通过穿通基板通孔（TSV）耦合的单独预制基板堆叠。 有源器件（AD）衬底在其上部具有接触。 隔离器衬底被结合到AD衬底上，使得隔离器衬底中的TSV耦合到AD衬底上的触点。 IPD衬底接合到隔离器衬底，使得其中的TSV耦合到隔离器衬底上的互连区和/或其中的TSV。 IPD基板的IPD通过IPD和隔离器基板中的TSV耦合到AD基板中的设备。 隔离器基板提供优异的IPD与AD串扰衰减，同时允许每个基板具有小的高纵横比TSV，从而有助于高电路封装密度和高效制造。

公开(公告)号：US09224704B2

公开(公告)日：2015-12-29

申请号：US13219099

申请日：2011-08-26

Applicant: Didier Landru

Inventor： Didier Landru

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/30 ,  H01L21/46 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0332 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05006 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05187 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05576 ,  H01L2224/05578 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/04941 ,  H01L2924/00

Abstract: The present invention relates to a process for realizing a connecting structure in a semiconductor substrate, and the semiconductor substrate realized accordingly. The semiconductor substrate has at least a first surface, and is foreseen for a 3D integration with a second substrate along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value. This process includes growing a diffusion barrier structure for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, wherein a first end surface, being the most outward surface of the diffusion barrier structure and being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure can have a length, in the direction of the lateral misalignment, the length being dependent on the misalignment value, wherein the length of the diffusion barrier structure is chosen such that in a 3D integrated structure a diffusion of elements out of a conductive layer of the second substrate is prevented in the integrated state.

Abstract translation: 本发明涉及实现半导体衬底中的连接结构的方法，并且相应地实现了半导体衬底。 半导体衬底具有至少第一表面，并且预期用于沿着第一表面与第二衬底的3D集成，其中3D积分在具有未对准值的至少一个维度中受到横向错位。 该方法包括生长扩散阻挡结构，用于防止元件从导电层扩散到半导体衬底的其余部分中，其中第一端面是扩散阻挡结构的最外表面，并且基本平行于第一表面 沿垂直于第一表面的方向并且从衬底朝着第一表面延伸的扩散阻挡结构的长度可以在横向不对准的方向上具有取决于不对准值的长度，其中， 扩散阻挡结构被选择为使得在3D集成结构中，元件在第二基板的导电层中的扩散在集成状态下被阻止。

公开(公告)号：US09214442B2

公开(公告)日：2015-12-15

申请号：US11688050

申请日：2007-03-19

Applicant: Karsten Guth ,  Holger Torwesten

Inventor： Karsten Guth ,  Holger Torwesten

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L24/32 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45647 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In a power semiconductor module, a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another. The connection layer has a portion of intermetallic copper-tin phases of at least 90% by weight. For producing such a power semiconductor module the soldering partners and the solder arranged there between are pressed against one another with a predefined pressure and the solder is melted. After termination of a predefined period of time the diffused copper and the tin from the liquid solder form a connection layer comprising intermetallic copper-tin phases, the portion of which is at least 90% by weight of the connection layer created from the solder layer.

Abstract translation: 在功率半导体模块中，连续并且固定地连接有含铜的第一焊接对象，连接层和含铜的第二焊接对象。 连接层具有至少90重量％的金属间铜 - 锡相的一部分。 为了制造这样的功率半导体模块，焊接对象和布置在其间的焊料彼此以预定压力彼此压紧，并且焊料熔化。 在预定时间段结束之后，扩散的铜和来自液态焊料的锡形成包含金属间铜 - 锡相的连接层，该连接层的至少90％是由焊料层形成的连接层。

公开(公告)号：US20150348925A1

公开(公告)日：2015-12-03

申请号：US14725242

申请日：2015-05-29

Applicant: APPLIED Materials, Inc.

Inventor： David P. Surdock ,  Marvin L. Bernt

IPC: H01L23/00

CPC classification number: H01L24/13 ,  C23F1/26 ,  C23F1/38 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/03831 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05609 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/11005 ,  H01L2224/11013 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/13006 ,  H01L2224/13018 ,  H01L2224/13027 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13563 ,  H01L2224/1357 ,  H01L2224/13666 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2224/0231 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/00012

Abstract: In accordance with one embodiment of the present disclosure, a method of forming a metal feature includes etching a portion of a first metal layer using a first etching chemistry, and etching a portion of a barrier layer using a second etching chemistry to achieve a barrier layer undercut of less than or equal to 2 times the thickness of the barrier layer.

Abstract translation: 根据本公开的一个实施例，形成金属特征的方法包括使用第一蚀刻化学法蚀刻第一金属层的一部分，并且使用第二蚀刻化学法蚀刻阻挡层的一部分以实现阻挡层 底切小于或等于阻挡层厚度的2倍。

公开(公告)号：US20150348877A1

公开(公告)日：2015-12-03

申请号：US14475169

申请日：2014-09-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chang-Chia Huang ,  Tsung-Shu Lin ,  Cheng-Chieh Hsieh ,  Wei-Cheng Wu

IPC: H01L23/488 ,  H01L23/00

CPC classification number: H01L24/06 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76885 ,  H01L23/3185 ,  H01L23/488 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05015 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05555 ,  H01L2224/06131 ,  H01L2224/06179 ,  H01L2224/06515 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81805 ,  H01L2224/83005 ,  H01L2224/838 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/3512 ,  H01L2924/35121

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Abstract translation: 提供了一种使用邻近接触焊盘的虚拟焊盘特征的装置和制造方法。 接触垫可以是集成扇出封装中的接触焊盘，其中模塑料沿着模具的侧壁放置，并且接触垫在模具和模塑料上延伸。 接触垫使用一个或多个再分配层电耦合到管芯。 虚拟焊盘特征与接触焊盘电隔离。 在一些实施例中，虚拟焊盘特征部分地环绕接触焊盘，并且位于模塑料的拐角区域中，模具的拐角区域和/或模具的边缘与模塑料之间的界面区域。