公开(公告)号：US08436478B2

公开(公告)日：2013-05-07

申请号：US12827476

申请日：2010-06-30

Applicant: Teck Kheng Lee

Inventor： Teck Kheng Lee

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1012 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81138 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/20105 ,  H01L2924/20106 ,  H05K3/06 ,  H05K3/325 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0315 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00012

Abstract: A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material, performing a first etching process on the layer of conductive material with the masking layer in place, removing the masking layer and, after removing the masking layer, performing an isotropic etching process on the layer of conductive material to thereby define a plurality of piercing bond structures positioned on the substrate.

Abstract translation: 公开了一种方法，其包括在衬底上形成导电材料层，在导电材料层之上形成掩模层，在掩蔽层就位的导电材料层上执行第一蚀刻工艺，去除掩模层和 在去除掩模层之后，对导电材料层进行各向同性蚀刻处理，从而限定位于基板上的多个穿孔接合结构。

公开(公告)号：US08420722B2

公开(公告)日：2013-04-16

申请号：US12476925

申请日：2009-06-02

Applicant: Yong Sung Eom ,  Jong Tae Moon ,  Sangwon Oh ,  Keonsoo Jang

Inventor： Yong Sung Eom ,  Jong Tae Moon ,  Sangwon Oh ,  Keonsoo Jang

IPC: B60C1/00

CPC classification number: H05K13/0465 ,  B23K3/0623 ,  B23K35/24 ,  B23K35/34 ,  B23K35/3601 ,  B23K35/3613 ,  B23K2101/36 ,  B82Y10/00 ,  H01L24/29 ,  H01L24/30 ,  H01L24/83 ,  H01L2224/1141 ,  H01L2224/1152 ,  H01L2224/1184 ,  H01L2224/16238 ,  H01L2224/27416 ,  H01L2224/2784 ,  H01L2224/3003 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81355 ,  H01L2224/83886 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/46 ,  H05K2201/026 ,  H05K2201/10977 ,  Y10T29/49117 ,  Y10T29/49126

Abstract: Provided are a composition for an anisotropic conductive adhesive, a method of forming a solder bump and a method of forming a flip chip using the same. The composition for an anisotropic conductive adhesive includes a low melting point solder particle and a thermo-curable polymer resin. The anisotropic conductive adhesive includes forming a mixture by mixing a polymer resin and a curing agent, and mixing a deforming agent, a catalyst or a reductant with the mixture.

公开(公告)号：US20130082089A1

公开(公告)日：2013-04-04

申请号：US13250297

申请日：2011-09-30

Applicant: Michael K. Gallagher ,  Kim S. Ho ,  Avin V. Dhoble ,  Mark R. Winkle ,  Xiang-Qian Liu ,  David Fleming

Inventor： Michael K. Gallagher ,  Kim S. Ho ,  Avin V. Dhoble ,  Mark R. Winkle ,  Xiang-Qian Liu ,  David Fleming

IPC: B23K35/363 ,  B23K31/02 ,  B23K1/20

CPC classification number: B23K1/0016 ,  B23K1/203 ,  C08K5/09 ,  C08K5/17 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/27418 ,  H01L2224/27422 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/9211 ,  H05K3/3436 ,  H05K3/3489 ,  H05K2201/10674 ,  H05K2201/10977 ,  C08L63/00 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A curable flux composition is provided, comprising, as initial components: a resin component having at least two oxirane groups per molecule; a carboxylic acid; a fluxing agent represented by formula I: wherein R1, R2, R3 and R4 are independently selected from a hydrogen, a substituted C1-80 alkyl group, an unsubstituted C1-80 alkyl group, a substituted C7-80 arylalkyl group and an unsubstituted C7-80 arylalkyl group; and wherein zero to three of R1, R2, R3 and R4 is(are) a hydrogen; and, optionally, a curing agent. Also provided is a method of soldering an electrical contact using the curable flux composition.

Abstract translation: 提供了一种可固化助焊剂组合物，其包含作为初始组分的树脂组分：每分子具有至少两个环氧乙烷基团的树脂组分; 羧酸; 由式I表示的助熔剂：其中R1，R2，R3和R4独立地选自氢，取代的C1-80烷基，未取代的C1-80烷基，取代的C7-80芳烷基和未取代的C7 -80芳烷基; 并且其中R 1，R 2，R 3和R 4中的0至3个为氢; 和任选的固化剂。 还提供了使用可固化焊剂组合物焊接电接触的方法。

公开(公告)号：US08391015B2

公开(公告)日：2013-03-05

申请号：US12357867

申请日：2009-01-22

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K7/00

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/112 ,  H05K3/305 ,  H05K2201/0175 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2201/10977

Abstract: A printed wiring board includes an insulating layer and a capacitor including a ceramic high dielectric layer being interposed between a first and a second electrode, and a semiconductor device mounting pad, including a first and a second pad, formed on an outermost resin insulating layer of the resin insulating layers. An underfill which covers an area larger than that of the high dielectric layer is formed, when the underfill covered area is projected along a lamination direction of the resin insulating layers to a face on which the high dielectric layer is formed. The capacitor is located immediately beneath the underfill covered area.

Abstract translation: 一种印刷线路板包括绝缘层和一个电容器，该电容器包括介于第一和第二电极之间的陶瓷高介电层，以及半导体器件安装衬垫，包括第一和第二衬垫，该衬底形成在第一和第二衬底的最外层树脂绝缘层上 树脂绝缘层。 当底层覆盖区域沿着树脂绝缘层的层叠方向突出到形成有高介电层的面时，形成覆盖比高介电层的面积大的面积的底部填充物。 电容器位于底部填充区域的正下方。

公开(公告)号：US08379395B2

公开(公告)日：2013-02-19

申请号：US12665735

申请日：2008-04-22

Applicant: Gerhard Wetzel

Inventor： Gerhard Wetzel

IPC: H05K1/00 ,  H05K1/18 ,  H05K7/00

CPC classification number: H05K3/284 ,  H01L23/3107 ,  H01L2924/0002 ,  H05K2201/1034 ,  H05K2201/10757 ,  H05K2201/10977 ,  H05K2203/1316 ,  H01L2924/00

Abstract: An electrical component system and method is provided. In an embodiment, the electrical component system includes a circuit carrier onto which at least one electrical component has been mounted. The circuit carrier is injection molded around using a molding compound. An embedding length of a circuit-board conductor in the molding compound, situated between the contacting area on the circuit carrier and the exit location, is maximized.

Abstract translation: 提供电气部件系统和方法。 在一个实施例中，电气部件系统包括其上安装有至少一个电气部件的电路载体。 使用模塑料将电路载体注塑成型。 位于电路载体上的接触区域和出口位置之间的模制化合物中的电路板导体的嵌入长度最大化。

公开(公告)号：US08378472B2

公开(公告)日：2013-02-19

申请号：US12738430

申请日：2008-10-16

Applicant: Koso Matsuno ,  Atsushi Yamaguchi ,  Shigeaki Sakatani ,  Hidenori Miyakawa ,  Mikiya Ueda

Inventor： Koso Matsuno ,  Atsushi Yamaguchi ,  Shigeaki Sakatani ,  Hidenori Miyakawa ,  Mikiya Ueda

IPC: H01L23/22

CPC classification number: H01L21/563 ,  H01L23/13 ,  H01L23/3121 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/15313 ,  H05K1/0224 ,  H05K3/28 ,  H05K3/3452 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/10977

Abstract: In order to easily inject underfill resin and perform molding with reliability, groove sections are formed on a surface of a circuit board such that the ends of the groove sections extend to semiconductor elements. Low-viscosity underfill resin applied dropwise is guided by the groove sections and flows between the circuit board and the semiconductor elements. The underfill resin hardly expands to regions outside the semiconductor elements.

Abstract translation: 为了容易地注入底部填充树脂并且可靠地进行模制，在电路板的表面上形成槽部，使得槽部的端部延伸到半导体元件。 滴下的低粘度底部填充树脂由槽部引导，在电路基板与半导体元件之间流动。 底部填充树脂几乎不扩展到半导体元件外部的区域。

公开(公告)号：US08285380B2

公开(公告)日：2012-10-09

申请号：US13429215

申请日：2012-03-23

Applicant: Robert J. Greenberg ,  Jerry Ok

Inventor： Robert J. Greenberg ,  Jerry Ok

IPC: A61N1/00

CPC classification number: A61N1/0543 ,  A61N1/36046 ,  A61N1/3752 ,  H01L23/057 ,  H01L23/10 ,  H01L23/4985 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/01079 ,  H01L2924/1461 ,  H05K1/0306 ,  H05K3/321 ,  H05K3/328 ,  H05K3/361 ,  H05K3/4015 ,  H05K3/423 ,  H05K3/4652 ,  H05K3/4691 ,  H05K2201/09127 ,  H05K2201/10287 ,  H05K2201/10295 ,  H05K2201/10977 ,  H05K2203/0733 ,  H05K2203/1446 ,  H01L2924/00

Abstract: The invention is directed to a method of bonding a hermetically sealed electronics package to an electrode or a flexible circuit and the resulting electronics package that is suitable for implantation in living tissue, such as for a retinal or cortical electrode array to enable restoration of sight to certain non-sighted individuals. The hermetically sealed electronics package is directly bonded to the flex circuit or electrode by electroplating a biocompatible material, such as platinum or gold, effectively forming a plated rivet-shaped connection, which bonds the flex circuit to the electronics package. The resulting electronic device is biocompatible and is suitable for long-term implantation in living tissue.

Abstract translation: 本发明涉及一种将气密密封的电子封装结合到电极或柔性电路的方法，以及所得的电子封装，其适于植入生物组织，例如用于视网膜或皮层电极阵列，以使视力恢复到 某些非目标人士。 密封电子封装通过电镀生物相容性材料（例如铂或金）直接结合到柔性电路或电极上，有效地形成电镀铆钉形连接，其将柔性电路连接到电子封装。 所得到的电子装置是生物相容的并且适合长期植入生物体组织。

公开(公告)号：US08283246B2

公开(公告)日：2012-10-09

申请号：US13091801

申请日：2011-04-21

Applicant: Takashi Kitae ,  Seiichi Nakatani ,  Seiji Karashima ,  Yoshihisa Yamashita ,  Takashi Ichiryu

Inventor： Takashi Kitae ,  Seiichi Nakatani ,  Seiji Karashima ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC: H01L21/00

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11001 ,  H01L2224/11003 ,  H01L2224/1141 ,  H01L2224/11502 ,  H01L2224/11522 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/165 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29299 ,  H01L2224/29305 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29316 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2224/832 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/8388 ,  H01L2224/83885 ,  H01L2224/83886 ,  H01L2224/83887 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0264 ,  H05K2203/087 ,  H05K2203/1178 ,  Y02P70/613 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/066 ,  H01L2924/06 ,  H01L2924/0675 ,  H01L2924/0695 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The invention involves mounting a solder resin composition (6) including a solder powder (5a) and a resin (4) on the first electronic component (2); arranging such that the connecting terminals (3) of the first electronic component (2) and the electrode terminals (7) of the second electronic component (8) are facing each other; ejecting a gas (9a) from a gas generation source (1) included in the first electronic component (2) by heating the first electronic component (2) and the solder resin composition; and inducing the flow of the solder powder (5a) in the solder resin composition (6) by inducing convection of the gas (9a) in the solder resin composition (6), and electrically connecting the connecting terminals (3) and the electrode terminals (7) by self-assembly on the connecting terminals (3) and the electrode terminals (7). Through this are provided a flip chip packaging method that enables connecting, with high connection reliability, electrode terminals of a semiconductor chip wired with narrow pitch and connecting terminals of a circuit board, and a bump formation method for packaging on a circuit board.

Abstract translation: 本发明涉及将包含焊料粉末（5a）和树脂（4）的焊料树脂组合物（6）安装在第一电子部件（2）上; 排列成使得第一电子部件（2）的连接端子（3）和第二电子部件（8）的电极端子（7）彼此面对; 通过加热第一电子部件（2）和焊料树脂组合物，从包括在第一电子部件（2）中的气体发生源（1）喷出气体（9a） 并且通过引起焊料树脂组合物（6）中的气体（9a）的对流而引起焊料粉末（5a）在焊料树脂组合物（6）中的流动，并将连接端子（3）和电极端子 （7）通过在连接端子（3）和电极端子（7）上的自组装。 通过这种方式提供了一种倒装芯片封装方法，其以高连接可靠性连接具有窄间距的半导体芯片的电极端子和电路板的连接端子，以及用于封装在电路板上的凸块形成方法。

公开(公告)号：US20120248616A1

公开(公告)日：2012-10-04

申请号：US13361344

申请日：2012-01-30

Applicant: Masayuki KITAJIMA ,  Takatoyo Yamakami ,  Takashi Kubota ,  Kuniko Ishikawa

Inventor： Masayuki KITAJIMA ,  Takatoyo Yamakami ,  Takashi Kubota ,  Kuniko Ishikawa

IPC: H01L23/48 ,  B23K35/24

CPC classification number: H05K3/3442 ,  B23K1/0016 ,  B23K1/206 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/0255 ,  B23K35/262 ,  B23K35/302 ,  B23K35/3613 ,  B23K2101/42 ,  C22C13/00 ,  H01L2924/0002 ,  H05K3/284 ,  H05K3/3484 ,  H05K2201/0323 ,  H05K2201/10977 ,  H05K2203/1476 ,  Y02P70/613 ,  H01L2924/00

Abstract: To provide an electronic component, containing: a wiring board containing electrode pads; a component including a plurality of electrodes, the component being mounted on the wiring board; a sealing resin covering the component; and a plurality of terminals configured to connect a wiring provided within the wiring board to an external substrate, wherein the plurality of electrodes and the electrode pads are connected with solder, and wherein a first resin layer and a second resin layer are provided between the solder and the sealing resin in this order from the side of the solder, where the first resin layer has a first Young's modulus and the second resin layer has a second Young's modulus larger than the first Young's modulus.

Abstract translation: 提供一种电子部件，其包含：包含电极焊盘的布线板; 包括多个电极的部件，所述部件安装在所述布线板上; 覆盖该部件的密封树脂; 以及多个端子，其被配置为将布线板内设置的布线与外部基板连接，其中所述多个电极和所述电极焊盘与焊料连接，并且其中在所述焊料之间设置有第一树脂层和第二树脂层 和密封树脂，其中第一树脂层具有第一杨氏模量，第二树脂层的第二杨氏模量大于第一杨氏模量。

公开(公告)号：US20120244666A1

公开(公告)日：2012-09-27

申请号：US13426687

申请日：2012-03-22

Applicant: Noriaki MUKAI ,  Masaru Mitsumoto ,  Makoto Homma

Inventor： Noriaki MUKAI ,  Masaru Mitsumoto ,  Makoto Homma

IPC: H01L21/56 ,  B23K37/00 ,  B32B38/04

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L23/564 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/73104 ,  H01L2224/75272 ,  H01L2224/75281 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8388 ,  H01L2224/83951 ,  H01L2224/9211 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/351 ,  H05K3/303 ,  H05K2201/0129 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T156/1304 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/3512 ,  H01L2924/00

Abstract: Solder bumps are formed on a plurality of electrode parts of a printed substrate and a semiconductor chip is loaded on the printed substrate via the plurality of solder bumps. In this case, a thermoplastic film is prepared as an underfill that covers a surface of the printed substrate on which the solder bumps are formed. In the film, parts corresponding to the solder bumps are removed and a peripheral edge of a part on which the semiconductor chip will be loaded has a protruded form. After the printed substrate has been covered with the film, the film is bonded onto the board and the semiconductor chip is loaded on the printed substrate and carried into a reflow furnace. In the reflow furnace, heat and pressure are applied to fuse the solder bumps.

Abstract translation: 在印刷基板的多个电极部分上形成焊料凸块，并且通过多个焊料凸块将半导体芯片装载到印刷基板上。 在这种情况下，制备热塑性膜作为覆盖形成有焊锡凸块的印刷基板的表面的底部填充物。 在薄膜中，除去对应于焊料凸点的部分，并且其上将加载半导体芯片的部分的外围边缘具有突出的形状。 在印刷基板被膜覆盖之后，将膜粘合到板上，并将半导体芯片装载在印刷基板上，并携带到回流炉中。 在回流炉中，施加热和压力来熔化焊料凸块。