Patent search cpc:"H01L2224/13599" Page 8

71.

发明申请
Bump Pad Structure 有权

公开(公告)号：US20130181347A1

公开(公告)日：2013-07-18

申请号：US13786045

申请日：2013-03-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Yi Tsai , Hsien-Wei Chen , Yu-Wen Liu , Ying-Ju Chen , Hsiu-Ping Wei

IPC: H01L23/48 , H01L21/768

CPC classification number: H01L24/05 , H01L21/768 , H01L21/76877 , H01L23/48 , H01L23/481 , H01L24/03 , H01L24/13 , H01L2224/0401 , H01L2224/05012 , H01L2224/0509 , H01L2224/05092 , H01L2224/05094 , H01L2224/05095 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/05599 , H01L2224/131 , H01L2924/00013 , H01L2924/00014 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012

Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.

72.

发明授权
Template wafer and process for small pitch flip-chip interconnect hybridization 失效
Title translation: 用于小间距倒装芯片互连杂交的模板晶片和工艺

公开(公告)号：US08456004B2

公开(公告)日：2013-06-04

申请号：US13414781

申请日：2012-03-08

Applicant: Justin K. Markunas , Eric F. Schulte

Inventor： Justin K. Markunas , Eric F. Schulte

IPC: H01L23/48 , H01L23/52 , H01L29/40

CPC classification number: H01L21/76885 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/742 , H01L2224/11003 , H01L2224/111 , H01L2224/11334 , H01L2224/13109 , H01L2224/16148 , H01L2224/742 , H01L2224/81203 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01027 , H01L2924/01033 , H01L2924/01049 , H01L2924/01072 , H01L2924/01078 , H01L2924/14 , H01L2924/01204 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599

Abstract: A process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used.

Abstract translation: 公开了一种通过使用最初制造凸起的创新模板晶片来实现微芯片的高密度铟凸起的工艺。一旦制造，这些凸块被转移到微芯片，之后可以与另一个微芯片杂交。这样的模板晶片是可重复使用的，因此提供了制造铟凸块的经济方法。可再利用性还消除了单独的微芯片的串联处理中的凸起形状和尺寸的不均匀性，对于其它铟凸块制造工艺不是这种情况。这种制造工艺提供了形成相对较高的铟凸块的方法，并且在没有标准的厚光致抗蚀剂剥离工艺的情况下实现了这一点。所描述的工艺可适用于10微米以下的凸起间距，并且仅受所使用的光刻设备的分辨率的限制。

73.

发明授权
Electroless plating of porous and non-porous nickel layers, and gold layer in semiconductor device 有权
Title translation: 多孔和无孔镍层的无电镀，以及半导体器件中的金层

公开(公告)号：US08455361B2

公开(公告)日：2013-06-04

申请号：US12943341

申请日：2010-11-10

Applicant: Juan Alejandro Herbsommer , Osvaldo Lopez

Inventor： Juan Alejandro Herbsommer , Osvaldo Lopez

IPC: H01L21/44

CPC classification number: H01L24/03 , H01L24/05 , H01L2224/03424 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05005 , H01L2224/05016 , H01L2224/05018 , H01L2224/05022 , H01L2224/05073 , H01L2224/05155 , H01L2224/05562 , H01L2224/05568 , H01L2224/05573 , H01L2224/05644 , H01L2224/13099 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/014 , H01L2924/14 , H01L2924/365 , H01L2924/01028 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552

Abstract: A method for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include sequentially electroless plating of each of the nickel layer and gold layer on the device layer to pre-determined thicknesses to prevent corrosion of the nickel layer from reaching the device layer during the electroless gold plating process.

Abstract translation: 一种用于在镍/金无电镀处理中在半导体器件的镍/钝化界面处维持无孔镍层的方法。该方法可以包括将器件层上的镍层和金层中的每一个顺序无电镀以预定的厚度，以防止在无电镀金工艺期间镍层的腐蚀到达器件层。

74.

发明授权
Photosensitive composition 有权
Title translation: 感光组合物

公开(公告)号：US08455175B2

公开(公告)日：2013-06-04

申请号：US13094629

申请日：2011-04-26

Applicant: Mark R. Winkle , Jill E. Steeper , Xiang-Qian Liu , Janet Okada-Coakley , Scott A. Ibbitson

Inventor： Mark R. Winkle , Jill E. Steeper , Xiang-Qian Liu , Janet Okada-Coakley , Scott A. Ibbitson

IPC: G03F7/027 , G03F7/028 , G03F7/033 , G03F7/09

CPC classification number: G03F7/033 , G03F7/161 , G03F7/162 , H01L24/11 , H01L2224/0345 , H01L2224/03464 , H01L2224/0401 , H01L2224/05647 , H01L2224/05655 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01038 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/0106 , H01L2924/01067 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00014 , H01L2924/01083 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599

Abstract: Photoresist compositions and methods suitable for depositing a thick photoresist layer in a single coating application are provided. Such photoresist layers are particularly suitable for use in chip scale packaging, for example, in the formation of metal bumps.

Abstract translation: 提供了适用于在单一涂层应用中沉积厚光致抗蚀剂层的光刻胶组合物和方法。这样的光致抗蚀剂层特别适用于芯片级封装，例如在金属凸块的形成中。

75.

发明授权
Method for manufacturing a semiconductor component 有权
Title translation: 半导体部件的制造方法

公开(公告)号：US08445375B2

公开(公告)日：2013-05-21

申请号：US12569732

申请日：2009-09-29

Applicant: Michael J. Seddon , Francis J. Carney

Inventor： Michael J. Seddon , Francis J. Carney

IPC: H01L21/44

CPC classification number: H01L23/53238 , H01L21/76885 , H01L23/3157 , H01L23/53252 , H01L23/58 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/48 , H01L2224/02126 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/11472 , H01L2224/11474 , H01L2224/11906 , H01L2224/11914 , H01L2224/13007 , H01L2224/13147 , H01L2224/13155 , H01L2224/13562 , H01L2224/13582 , H01L2224/13583 , H01L2224/13584 , H01L2224/136 , H01L2224/13611 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: A semiconductor component and methods for manufacturing the semiconductor component that includes a double exposure of a layer of photoresist or the use of multiple layers of photoresist. A metallization structure is formed on a layer of electrically conductive material that is disposed on a substrate and a layer of photoresist is formed on the metallization structure. The layer of photoresist is exposed to light and developed to remove a portion of the photoresist layer, thereby forming an opening. Then, a larger portion of the photoresist layer is exposed to light and an electrically conductive interconnect is formed in the opening. The larger portion of the photoresist layer that was exposed to light is developed to expose edges of the electrically conductive interconnect and portions of the metallization structure. A protection layer is formed on the top and edges of the electrically conductive interconnect and on the exposed portions of the metallization structure.

Abstract translation: 一种半导体部件和用于制造半导体部件的方法，包括光致抗蚀剂层的双重曝光或多层光致抗蚀剂的使用。金属化结构形成在导电材料层上，该导电材料层设置在基板上，并且在金属化结构上形成光刻胶层。将光致抗蚀剂层暴露于光并显影以除去光致抗蚀剂层的一部分，从而形成开口。然后，光致抗蚀剂层的较大部分暴露于光，并且在开口中形成导电互连。显影光致抗蚀剂层的较大部分被曝光以暴露导电互连件的边缘和金属化结构的部分。在导电互连的顶部和边缘以及金属化结构的暴露部分上形成保护层。

76.

发明授权
Integrated circuit packaging system with flipchip leadframe and method of manufacture thereof 有权
Title translation: 具有倒装引线框的集成电路封装系统及其制造方法

公开(公告)号：US08420447B2

公开(公告)日：2013-04-16

申请号：US13070291

申请日：2011-03-23

Applicant: Lionel Chien Hui Tay , Henry Descalzo Bathan , Zigmund Ramirez Camacho

Inventor： Lionel Chien Hui Tay , Henry Descalzo Bathan , Zigmund Ramirez Camacho

IPC: H01L21/50

CPC classification number: H01L23/49575 , H01L23/3107 , H01L23/49524 , H01L23/49558 , H01L23/49861 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/131 , H01L2224/14131 , H01L2224/16225 , H01L2224/16245 , H01L2224/32145 , H01L2224/48227 , H01L2224/48245 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2225/06558 , H01L2225/1029 , H01L2225/1041 , H01L2225/1058 , H01L2225/1088 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2924/00 , H01L2924/00012 , H01L2224/32225 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: leads and a paddle; a first encapsulant molded between the leads and the paddle, the first encapsulant thinner than the leads; a non-conductive layer over the paddle; and conductive traces directly on the leads, the first encapsulant, and the non-conductive layer.

Abstract translation: 集成电路封装系统及其制造方法包括：引线和桨; 模制在引线和桨之间的第一密封剂，第一密封剂比引线更薄; 在桨上的非导电层; 导电迹线直接在引线，第一密封剂和非导电层上。

77.

发明授权
Integrated circuit packaging system with lead frame etching and method of manufacture thereof 有权
Title translation: 具有引线框架蚀刻的集成电路封装系统及其制造方法

公开(公告)号：US08415206B2

公开(公告)日：2013-04-09

申请号：US13070899

申请日：2011-03-24

Applicant: Zigmund Ramirez Camacho

Inventor： Zigmund Ramirez Camacho

IPC: H01L21/00

CPC classification number: H01L23/49582 , H01L21/4828 , H01L21/568 , H01L23/3107 , H01L23/49548 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L2224/32245 , H01L2224/48177 , H01L2224/48245 , H01L2224/48247 , H01L2224/49052 , H01L2224/73265 , H01L2224/85439 , H01L2224/85444 , H01L2224/85455 , H01L2924/00013 , H01L2924/00014 , H01L2924/12042 , H01L2924/181 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a pre-plated leadframe having a contact pad and a die paddle pad; forming an isolated contact from the pre-plated leadframe and the contact pad; mounting an integrated circuit die over the die paddle pad; and encapsulating with an encapsulation the integrated circuit die and the isolated contact, the encapsulation having a bottom surface which is planar and exposing in the bottom surface only the contact pad and the die paddle pad.

Abstract translation: 一种集成电路封装系统的制造方法，包括：提供具有接触焊盘和管芯焊盘的预镀引线框架; 从预镀引线框架和接触焊盘形成隔离接触; 将集成电路管芯安装在管芯焊盘上; 并且用封装封装集成电路管芯和隔离接触件，该封装件具有平坦的底表面，并且在底部表面仅露出接触焊盘和管芯焊盘。

78.

发明授权
Integrated circuit packaging system with multiple row leads and method of manufacture thereof 有权
Title translation: 具有多排引线的集成电路封装系统及其制造方法

公开(公告)号：US08377750B2

公开(公告)日：2013-02-19

申请号：US12968266

申请日：2010-12-14

Applicant: Zigmund Ramirez Camacho , Dioscoro A. Merilo , Henry Descalzo Bathan

Inventor： Zigmund Ramirez Camacho , Dioscoro A. Merilo , Henry Descalzo Bathan

IPC: H01L21/00 , H01L23/495

CPC classification number: H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32245 , H01L2224/48247 , H01L2224/48257 , H01L2224/49171 , H01L2224/73265 , H01L2224/92247 , H01L2924/00013 , H01L2924/00014 , H01L2924/10162 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base structure having a die paddle, an outer lead, and an inner lead between the die paddle and the outer lead, with a pre-plated finish on a base structure system side of the base structure; mounting an integrated circuit device to a side of the die paddle opposite the paddle system side; attaching an interconnect to the integrated circuit device and a side of the inner lead opposite the inner lead system side; applying an encapsulation around the integrated circuit device, the interconnect, and the base structure with the pre-plated finish exposed from the encapsulation; and forming an inward channel in the encapsulation to electrically isolate the inner lead.

Abstract translation: 一种集成电路封装系统的制造方法，其特征在于，在基板结构系统侧，形成具有模板，外引线和芯片和外引线之间的内引线的基体结构的基础结构; 将集成电路装置安装在与所述桨叶系统侧相对的所述模桨的一侧; 将互连件连接到集成电路器件和内引线的与内引线系统侧相对的一侧; 在集成电路器件，互连和基底结构周围施加封装，其中从封装暴露出的预镀完成; 以及在所述封装中形成向内的沟道，以使所述内部引线电隔离。