公开(公告)号：US06737307B2

公开(公告)日：2004-05-18

申请号：US10185034

申请日：2002-06-28

申请人： Po-Hao Tsai ,  Nai-Hao Kuo ,  Wen-Jiun Liu ,  Yuh-Wen Lee

发明人： Po-Hao Tsai ,  Nai-Hao Kuo ,  Wen-Jiun Liu ,  Yuh-Wen Lee

IPC分类号： H01L2100

CPC分类号： H01L21/32055 ,  H01L21/28556 ,  H01L21/3205

摘要： A method for forming amorphous silicon films with low defect density on single crystal silicon substrates and structures formed. The method is carried out by first providing a single crystal silicon substrate, then depositing a buffer layer by a material such as silicon oxide, silicon nitride, silicon carbide or a metal on top of the single crystal silicon substrate. An amorphous silicon film of substantial thickness, i.e. of thicker than 1 &mgr;m, is then deposited on top of the buffer layer achieving a smooth top surface.

公开(公告)号：US07125795B2

公开(公告)日：2006-10-24

申请号：US10992709

申请日：2004-11-22

申请人： Nai-Hao Kuo ,  Kai-Hsiang Yen ,  Jing-Hung Chiou ,  Po-Hao Tsai ,  Yuh-Wen Lee

发明人： Nai-Hao Kuo ,  Kai-Hsiang Yen ,  Jing-Hung Chiou ,  Po-Hao Tsai ,  Yuh-Wen Lee

IPC分类号： H01L21/4763

CPC分类号： B81C1/00619 ,  G01P15/0802

摘要： A fabrication method for microstructures with high aspect ratios uses a CMOS process to form a desired microstructure on a silicon substrate. The steps of forming a contact plug and a via plug of the process are used to form etching channels in insulation layers, polysilicon layers and metal layers, penetrating to the silicon substrate. An etching process is then performed through the etching channel to form the desired microstructure with high aspect ratio.

摘要翻译： 具有高纵横比的微结构的制造方法使用CMOS工艺在硅衬底上形成期望的微结构。 形成该工艺的接触塞和通孔的步骤用于在绝缘层，多晶硅层和金属层中形成穿透到硅衬底的蚀刻通道。 然后通过蚀刻通道进行蚀刻工艺以形成具有高纵横比的所需微结构。

公开(公告)号：US20050064650A1

公开(公告)日：2005-03-24

申请号：US10992709

申请日：2004-11-22

申请人： Nai-Hao Kuo ,  Kai-Hsiang Yen ,  Jing-Hung Chiou ,  Po-Hao Tsai ,  Yuh-Wen Lee

发明人： Nai-Hao Kuo ,  Kai-Hsiang Yen ,  Jing-Hung Chiou ,  Po-Hao Tsai ,  Yuh-Wen Lee

IPC分类号： B81C99/00 ,  G01P15/08 ,  H01L21/8238

CPC分类号： B81C1/00619 ,  G01P15/0802

摘要： A fabrication method for microstructures with high aspect ratios uses a CMOS process to form a desired microstructure on a silicon substrate. The steps of forming a contact plug and a via plug of the process are used to form etching channels in insulation layers, polysilicon layers and metal layers, penetrating to the silicon substrate. An etching process is then performed through the etching channel to form the desired microstructure with high aspect ratio.

摘要翻译： 具有高纵横比的微结构的制造方法使用CMOS工艺在硅衬底上形成期望的微结构。 形成该工艺的接触塞和通孔的步骤用于在绝缘层，多晶硅层和金属层中形成穿透到硅衬底的蚀刻通道。 然后通过蚀刻通道进行蚀刻工艺以形成具有高纵横比的所需微结构。

公开(公告)号：US06804443B2

公开(公告)日：2004-10-12

申请号：US10601647

申请日：2003-06-24

申请人： Po-Hao Tsai ,  Jing-Hung Chiou ,  Kai-Hsiang Yen ,  Wen-Jiun Liu ,  Yuh-Wen Lee

发明人： Po-Hao Tsai ,  Jing-Hung Chiou ,  Kai-Hsiang Yen ,  Wen-Jiun Liu ,  Yuh-Wen Lee

IPC分类号： G02B610

CPC分类号： G02B6/132 ,  G02B2006/12176

摘要： Test structure and method of step coverage for optical waveguide production are disclosed. It combines the steps of producing the optical waveguide and the testing structure by forming the optical waveguide components on the chip and the test structure in the surrounding areas, so the optical waveguide and the test structure have the same upper covering layer. Etching solution is used for the etch testing of the test structure, and the step coverage of the upper covering layer for the optical waveguide is extrapolated by the etching result.

摘要翻译： 公开了用于光波导生产的步骤覆盖的测试结构和方法。 它结合了通过在芯片上形成光波导部件和周围区域的测试结构来生产光波导和测试结构的步骤，因此光波导和测试结构具有相同的上覆盖层。 蚀刻溶液用于测试结构的蚀刻测试，并且通过蚀刻结果外推了用于光波导的上覆盖层的台阶覆盖。

公开(公告)号：US08816498B2

公开(公告)日：2014-08-26

申请号：US13189127

申请日：2011-07-22

申请人： Cheng-Chieh Hsieh ,  Cheng-Lin Huang ,  Po-Hao Tsai ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Shin-Puu Jeng

发明人： Cheng-Chieh Hsieh ,  Cheng-Lin Huang ,  Po-Hao Tsai ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Shin-Puu Jeng

IPC分类号： H01L23/485 ,  H01L21/768

摘要： A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

公开(公告)号：US20110304042A1

公开(公告)日：2011-12-15

申请号：US12846260

申请日：2010-07-29

申请人： Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

发明人： Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05099 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13578 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1369 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.

摘要翻译： 工件包括具有顶表面和侧壁的铜凸块。 在铜凸块的侧壁而不是顶表面上形成保护层。 保护层包括铜和聚合物的化合物，并且是介电层。

公开(公告)号：US20110254160A1

公开(公告)日：2011-10-20

申请号：US12762085

申请日：2010-04-16

申请人： Po-Hao Tsai ,  Jing-Cheng Lin ,  Chen-Hua Yu

发明人： Po-Hao Tsai ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC分类号： H01L23/538

CPC分类号： H01L23/3121 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00 ,  H01L2224/81805

摘要： A device includes an interposer including a substrate having a top surface and a bottom surface. A plurality of through-substrate vias (TSVs) penetrates through the substrate. The plurality of TSVs includes a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension. An interconnect structure is formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs.

摘要翻译： 一种器件包括具有顶表面和底表面的衬底的插入器。 多个穿通基板通孔（TSV）穿过基板。 多个TSV包括具有第一长度和第一水平尺寸的第一TSV和具有不同于第一长度的第二长度的第二TSV和与第一水平尺寸不同的第二水平尺寸。 互连结构形成在衬底的顶表面上并电耦合到多个TSV。

公开(公告)号：US09024438B2

公开(公告)日：2015-05-05

申请号：US13192756

申请日：2011-07-28

申请人： Cheng-Lin Huang ,  I-Ting Chen ,  Ying Ching Shih ,  Po-Hao Tsai ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Cheng-Lin Huang ,  I-Ting Chen ,  Ying Ching Shih ,  Po-Hao Tsai ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/498 ,  H01L21/60 ,  H01L23/00

CPC分类号： H01L24/14 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/13011 ,  H01L2224/13014 ,  H01L2224/13078 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1405 ,  H01L2224/14051 ,  H01L2224/145 ,  H01L2224/16238 ,  H01L2224/17107 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81897 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01053 ,  H01L2924/01079 ,  H01L2924/01051 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A conductive bump structure of a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprises a regular body, and each of a second subset of the conductive bumps comprises a ring-shaped body.

摘要翻译： 半导体器件的导电凸块结构包括包括主表面的衬底和分布在衬底的主表面上的导电凸块。 导电凸块的第一子集中的每一个包括规则体，并且导电凸块的第二子集中的每一个包括环形体。

公开(公告)号：US08970035B2

公开(公告)日：2015-03-03

申请号：US13624356

申请日：2012-09-21

申请人： Jing-Cheng Lin ,  Po-Hao Tsai

发明人： Jing-Cheng Lin ,  Po-Hao Tsai

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/11 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/06102 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11612 ,  H01L2224/11614 ,  H01L2224/1182 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/14155 ,  H01L2224/14156 ,  H01L2224/14177 ,  H01L2224/14515 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16168 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01108 ,  H01L2224/11 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/00

摘要： A package structure includes a first substrate bonded to a second substrate by Connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar.

摘要翻译： 封装结构包括通过将第一基板上的金属柱连接到第二基板上的连接器而将第一基板接合到第二基板。 第一金属柱形成在第一衬底的第一区域上并覆盖并电连接到金属焊盘，第二金属柱形成在第一衬底的第二区域中的钝化层上。 在金属柱和第一连接器之间形成第一焊接区域，在第二金属柱和第二连接器之间形成第二焊点区域。 第一金属柱的厚度大于第二金属柱的厚度。

公开(公告)号：US08953336B2

公开(公告)日：2015-02-10

申请号：US13412958

申请日：2012-03-06

申请人： Chin-Fu Kao ,  Wen-Chih Chiou ,  Jing-Cheng Lin ,  Cheng-Lin Huang ,  Po-Hao Tsai

发明人： Chin-Fu Kao ,  Wen-Chih Chiou ,  Jing-Cheng Lin ,  Cheng-Lin Huang ,  Po-Hao Tsai

IPC分类号： H05K7/10

CPC分类号： H01L24/14 ,  H01L22/32 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14515 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014

摘要： A surface metal wiring structure for a substrate includes one or more functional μbumps formed of a first metal and an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps. The surface metal wiring structure also includes a plurality of sacrificial μbumps formed of the first metal that are electrically connected to the electrical test pads, where the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps.

摘要翻译： 用于基板的表面金属布线结构包括由第一金属形成的一个或多个功能性μ凸块和由用于接收电测试探针并电连接到所述一个或多个功能性μ凸起的第二金属形成的电测试垫。 表面金属布线结构还包括由第一金属形成的多个牺牲μ凸块，其电连接到电测试焊盘，其中牺牲μ凸块位于比一个或多个功能性μ凸块更靠近电测试垫的位置。