摘要:
A lead-free, antimony-free solder alloy comprising: (a) from 1 to 4 wt.% silver (b) from 0.5 to 6 wt.% bismuth (c) from 3.55 to 15 wt.% indium (d) 3 wt.% or less of copper (e) optionally one or more of the following elements 0 to 1 wt.% nickel 0 to 1 wt.% of titanium 0 to 1 wt.% manganese 0 to 1 wt.% of rare earths, such as cerium 0 to 1 wt.% of chromium 0 to 1 wt.% germanium 0 to 1 wt.% of gallium 0 to 1 wt.% of cobalt 0 to 1 wt.% of iron 0 to 1 wt.% of aluminum 0 to 1 wt.% of phosphorus 0 to 1 wt.% of gold 0 to 1 wt.% of tellurium 0 to 1 wt.% of selenium 0 to 1 wt.% of calcium 0 to 1 wt.% of vanadium 0 to 1 wt.% of molybdenum 0 to 1 wt.% of platinum 0 to 1 wt.% of magnesium (f) the balance tin, together with any unavoidable impurities.
摘要:
Metallpaste enthaltend (A) 75 bis 90 Gew.-% wenigstens eines Metalls, das in Form von Partikeln vorliegt, die ein Coating aufweisen, das wenigstens eine organische Verbindung enthält, (B) 0 bis 12 Gew.-% wenigstens eines Metallprecursors, (C) 6 bis 20 Gew.-% eines Gemischs mindestens zweier organischer Lösemittel und (D) 0 bis 10 Gew.-% wenigstens eines Sinterhilfsmittels, dadurch gekennzeichnet, dass das Lösemittelgemisch (C) zu 30 bis 60 Gew.-% aus mindestens einem mit Ausnahme einer Methylsubsitution am vorletzten C-Atom unsubstituierten 1-Hydroxyalkan mit 16-20 C-Atomen besteht.
摘要:
A lead-free, antimony-free solder alloy comprising: (a) from 1 to 4 wt.% silver (b) from 0.5 to 6 wt.% bismuth (c) from 3.55 to 15 wt.% indium (d) 3 wt.% or less of copper (e) optionally one or more of the following elements 0 to 1 wt.% nickel 0 to 1 wt.% of titanium 0 to 1 wt.% manganese 0 to 1 wt.% of rare earths, such as cerium 0 to 1 wt.% of chromium 0 to 1 wt.% germanium 0 to 1 wt.% of gallium 0 to 1 wt.% of cobalt 0 to 1 wt.% of iron 0 to 1 wt.% of aluminum 0 to 1 wt.% of phosphorus 0 to 1 wt.% of gold 0 to 1 wt.% of tellurium 0 to 1 wt.% of selenium 0 to 1 wt.% of calcium 0 to 1 wt.% of vanadium 0 to 1 wt.% of molybdenum 0 to 1 wt.% of platinum 0 to 1 wt.% of magnesium (f) the balance tin, together with any unavoidable impurities.
摘要:
L'invention concerne un procédé d'assemblage par adhésion moléculaire d'un premier substrat et d'un deuxième substrat selon des faces de contact, la face de contact du premier substrat présentant une couche électriquement conductrice sur au moins une partie de sa surface, le procédé comprenant les étapes suivantes : - dépôt d'une couche de liaison sur au moins une partie de la couche électriquement conductrice, ladite couche de liaison étant apte à assurer une adhésion moléculaire avec une zone de la face de contact du deuxième substrat et apte à se combiner avec la couche électriquement conductrice pour former un alliage conducteur, - mise en contact et collage par adhésion moléculaire de la couche de liaison du premier substrat avec la zone de la face de contact du deuxième substrat, - transformation, sur tout ou partie de son épaisseur, de tout ou partie de la couche électriquement conductrice avec tout ou partie de la couche de liaison et avec au moins une partie de l'épaisseur de la zone de la face de contact sur tout ou partie de la surface du deuxième substrat pour former une zone d'alliage(s) conducteur(s).
摘要:
A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.
摘要:
Die Erfindung betrifft ein elektronisches Bauteil sowie einen Halbleiterwafer und einen Bauteilträger zur Herstellung des Bauteils. Das elektronische Bauteil weist dazu einen Halbleiterchip (1) mit einer eine integrierte Schaltung aufweisenden Chipoberseite (2) und einer Chiprückseite (3) auf, wobei die Chiprückseite (3) eine magnetische Schicht (7) hat. Außerdem weist ein Chipträger an seiner Trägeroberseite (5) ebenfalls eine magnetische Schicht (8) auf. Mindestens eine der beiden Schichten (7, 8) ist permanentmagnetisch, so dass der Halbleiterchip auf dem Chipträger (5) magnetisch fixiert ist.
摘要:
A microelectronic assembly (10, 110, 210, 310, 410) includes a first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) having a first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) and a second substrate (14, 114, 214, 314, 414) having a second conductive element (26, 126, 226, 326, 426). The assembly further includes an electrically conductive alloy mass (16, 116) joined to the first and second conductive elements (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022), including a first, a second and a third material. First and second materials of the alloy mass (16, 116) each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) to a relatively lower amount toward the second conductive element (26, 126, 226, 326, 426), and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element (26, 126, 226, 326, 426) to a relatively lower amount toward the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022). The microelectronic assembly (10, 110, 210, 310, 410) is formed by aligning the first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912), having a first bond component (30, 230, 330, 430), with the second substrate (14, 114, 214, 314, 414), having a second bond component (40, 240, 340, 440), such that the first (30, 230, 330, 430, 1030) and second (40, 240, 340, 440) bond components are in contact with each other, the first bond component (30, 230, 330, 430, 1030) including a first material layer (36, 536, 636, 736, 836, 936) adjacent the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) and a first protective layer (38, 538, 638, 738, 838, 938) overlying the first material layer (36, 536, 636, 736, 836, 936), the second bond component (40, 240, 340, 440) including a second material layer (46) adjacent the second conductive element (26) and a second protective layer (48) overlying the second material layer (46), and heating the first (30, 230, 330, 430, 1030) and second (40, 240, 340, 440) bond components such that at least portions of the first (36, 536, 636, 736, 836, 936) and second (46) material layers diffuse together to form the alloy mass (16, 116) joining the first (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) and second (14, 114, 214, 314, 414) substrates with one another. There may be formed a plurality of first conductive elements (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) on the first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) and a plurality of second conductive elements (26, 126, 226, 326, 426) on the second substrate (14, 114, 214, 314, 414), joined by a plurality of conductive alloy masses (16, 116). The conductive alloy mass (116) may also surround and hermetically seal an internal volume.
摘要:
A semiconductor chip assembly and a method for forming the same are provided. The semiconductor chip assembly comprises: a semiconductor chip (20), a substrate (10), a first layer (203) formed on a surface of the substrate (10), in which one of the first layer (203) and the second layer (204) has an opening (205) therein; and a second layer (204) formed on a surface of the semiconductor chip (20) and connected to the first layer (203) by eutectic bonding.
摘要:
A bonding element includes a first transient liquid phase (TLP) bonding element including a first material and a second material, the first material having a higher melting point than the second material, a ratio of a quantity of the first material and the second material in the first TLP bonding element having a first value and a second TLP bonding element including the first material and the second material, a ratio of a quantity of the first material and the second material in the second TLP bonding element having a second value different from the first value.
摘要:
A method that in one embodiment is useful in bonding a first substrate (103) to a second substrate (303) includes forming a layer including metal over the first substrate. The layer including metal in one embodiment surrounds a semiconductor device, which can be a micro electromechanical system (MEMS) device. On the second substrate (303) is formed a first layer comprising silicon (401). A second layer (403) comprising germanium and silicon is formed on the first layer. A third layer (405) comprising germanium is formed on the second layer. The third layer is brought into contact with the layer including metal. Heat (and pressure in some embodiments) is applied to the third layer and the layer including metal to form a mechanical bond material between the first substrate and the second substrate in which the mechanical bond material is electrically conductive. In the case of the mechanical bond surrounding a semiconductor device such as a MEMS, the mechanical bond can be particularly advantageous as a hermetic seal for protecting the MEMS.