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    Semiconductor device having chip-on-chip structure, and semiconductor chip used therefor
    96.
    发明授权
    Semiconductor device having chip-on-chip structure, and semiconductor chip used therefor 失效
    具有片上芯片结构的半导体器件和用于其的半导体芯片

    公开(公告)号：US06635969B1

    公开(公告)日：2003-10-21

    申请号：US09511104

    申请日：2000-02-23

    申请人： Tomofumi Nakamura

    发明人： Tomofumi Nakamura

    IPC分类号： H01L2348

    CPC分类号： H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2924/10253 ,  H01L2924/00

    摘要： A semiconductor device having a chip-on-chip structure including a first semiconductor chip having a connecting member formed on its surface, and a second semiconductor chip overlapped with and joined to the surface of the first semiconductor chip and having a connecting member adhering to the connecting member in the first semiconductor chip on its surface opposite to the first semiconductor chip. An inter-chip sealing layer is provided between the first semiconductor chip and the second semiconductor chip. The connecting members may be respectively bumps formed in a raised state on the surfaces of the first semiconductor chip and the second semiconductor chip.

    摘要翻译： 一种具有片上芯片结构的半导体器件，包括：具有形成在其表面上的连接部件的第一半导体芯片;以及与第一半导体芯片的表面重叠并接合的第二半导体芯片， 连接构件在与第一半导体芯片相对的表面上的第一半导体芯片中。 在第一半导体芯片和第二半导体芯片之间设置芯片间密封层。 连接构件可以分别在第一半导体芯片和第二半导体芯片的表面上以升高状态形成凸起。

    Method of mounting electronic component on substrate without generation of voids in bonding material
    98.
    发明申请
    Method of mounting electronic component on substrate without generation of voids in bonding material 有权
    将电子部件安装在基板上而不在接合材料中产生空隙的方法

    公开(公告)号：US20030051905A1

    公开(公告)日：2003-03-20

    申请号：US10073106

    申请日：2002-02-12

    申请人： Fujitsu Limited

    发明人： Tsuyoshi Yamamoto ,  Mitsuo Suehiro ,  Hiroshi Yamada

    IPC分类号： H05K003/34

    CPC分类号： H05K3/305 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/73103 ,  H01L2224/73204 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/0129 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0182 ,  H05K2203/0475 ,  H05K2203/1105 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49169 ,  H01L2924/00012

    摘要： When an electronic component is mounted on a substrate, the electronic component is first placed on the substrate with a solid support interposed between the electronic component and the substrate. The solid support serves to space a terminal conductor of the electronic component from a corresponding terminal pad on the substrate. A conductive bonding material is then melted on the terminal pad. The melted conductive bonding material gets exposed to the peripheral atmosphere over a larger area. Even if a bubble is generated within the melted conductive bonding material, the bubble is allowed to easily get out of the melted conductive bonding material. Removal of the gas is promoted in the melted conductive bonding material. The solid support is subsequently melted. The electronic component is moved down toward the substrate, thereby contacting the terminal conductor with the melted conductive bonding material on the corresponding terminal pad. Removal of the gas in this manner leads to improvement in the strength of bonding between the substrate and the electronic component.

    摘要翻译： 当将电子部件安装在基板上时，首先将电子部件放置在基板上，并将固体支撑体插入在电子部件和基板之间。 固体支撑件用于将电子部件的端子导体从衬底上的对应的端子焊盘放置。 导电接合材料然后在端子焊盘上熔化。 熔融的导电接合材料在较大的面积上暴露于周围的气氛。 即使在熔融的导电接合材料内产生气泡，也允许气泡容易地从熔融的导电接合材料中脱出。 在熔融的导电接合材料中促进除去气体。 固体支持物随后熔化。 电子部件朝向基板移动，从而使端子导体与相应的端子焊盘上的熔融的导电接合材料接触。 以这种方式去除气体导致基板和电子部件之间的结合强度的改善。

    Process for producing a sealing and mechanical strength ring between a substrate and a chip hybridized by bumps on the substrate
    100.
    发明授权
    Process for producing a sealing and mechanical strength ring between a substrate and a chip hybridized by bumps on the substrate 有权
    用于在衬底和由衬底上的凸块杂交的芯片之间产生密封和机械强度环的方法

    公开(公告)号：US06238951B1

    公开(公告)日：2001-05-29

    申请号：US09298696

    申请日：1999-04-23

    申请人： Patrice Caillat

    发明人： Patrice Caillat

    IPC分类号： H01L2144

    CPC分类号： H01L24/81 ,  H01L23/10 ,  H01L2224/13109 ,  H01L2224/16108 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00012

    摘要： Process for the production of a sealing and mechanical strength ring between a substrate and a chip hybridized by bumps on the substrate. The invention provides a process for producing an encapsulating ring (13) ensuring the sealing and mechanical strength of a chip (1) hybridized by bumps on a substrate (5). More particularly, contemporaneously with the production of the hybridization bumps (9) on the lower face (1a) of the chip or the substrate by a first meltable material, a sealing and mechanical strength ring is formed by depositing on the substrate or lower face of the electronic component a ring (13) of a second meltable material. The lower face of the chip then is placed on the substrate so as to produce the connections between said chip and said substrate by means of the first meltable material, and the thus formed assembly is heated to a temperature at least equal to the highest melting point of the first and second meltable materials, in order simultaneously to produce the hybridization bumps of the first material and the sealing ring of the second material. The ring is sized to have a height (h) and a width (d) in accordance with the following equation: d > 10 - 2 ⁢ D × h h - α in which &agr; is a shape coefficient factor and D is the largest dimension of the electronic component.

    摘要翻译： 用于在衬底和由衬底上的凸块杂交的芯片之间生产密封和机械强度环的方法。 本发明提供了一种用于制造密封环（13）的方法，该密封环确保与衬底（5）上的凸块杂交的芯片（1）的密封和机械强度。 更具体地，通过第一可熔材料在芯片或基板的下表面（1a）上产生杂交凸块（9）的同时，密封和机械强度环通过沉积在基板或底板 所述电子部件是第二可熔材料的环（13）。 然后将芯片的下表面放置在基板上，以便通过第一可熔材料产生所述芯片和所述基板之间的连接，并将由此形成的组件加热至至少等于最高熔点的温度 的第一和第二可熔化材料，以便同时产生第一材料和第二材料的密封环的杂交凸块。 该环的大小根据以下等式具有高度（h）和宽度（d）：其中α是形状系数因子，D是电子部件的最大尺寸。