Semiconductor interconnect having test structures for evaluating
electrical characteristics of the interconnect
    121.
    发明授权
    Semiconductor interconnect having test structures for evaluating electrical characteristics of the interconnect 失效
    半导体互连具有用于评估互连的电特性的测试结构

    公开(公告)号:US5838161A

    公开(公告)日:1998-11-17

    申请号:US640472

    申请日:1996-05-01

    CPC classification number: G01R31/2884 G01R35/00 G01R1/0408 G01R31/2818

    Abstract: An interconnect for a semiconductor die includes integrally formed test structures for evaluating various electrical characteristics of the interconnect. The test structures can include Kelvin structures, van der Pauw structures, resistors, capacitors, contact chains, via chains, serpentine test structures, and antenna test structures. Among the electrical characteristics that can be evaluated are the resistivity of contact member, conductor and substrate components of the interconnect, contact resistance between the contact members and conductors and capacitance of the contact members and conductors with respect to the substrate.

    Abstract translation: 用于半导体管芯的互连件包括用于评估互连的各种电特性的整体形成的测试结构。 测试结构可以包括开尔文结构,范德堡结构,电阻,电容器,接触链,通孔链,蛇形测试结构和天线测试结构。 可以评估的电气特性是互连部件的接触部件,导体和基板部件的电阻率,接触部件和导体之间的接触电阻以及接触部件和导体相对于基板的电容。

    Temporary connection of semiconductor die using optical alignment
techniques
    123.
    发明授权
    Temporary connection of semiconductor die using optical alignment techniques 失效
    使用光学对准技术临时连接半导体芯片

    公开(公告)号:US5483174A

    公开(公告)日:1996-01-09

    申请号:US192391

    申请日:1994-02-03

    Abstract: Optical alignment techniques, such as those used in "flip chip" bonding, are used to establish ohmic contact with the die by means of raised portions on contact members. This permits accurate alignment with a temporary die fixture in order to test the die. The tested die can then be qualified under a known good die program as having an acceptable degree of reliability. This permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. The ohmic contact is preferably established by applying a compression force applied to the die against the substrate results in a limited penetration of the contact member into the bondpads. The arrangement may be used for establishing electrical contact and with a burn-in oven and with a discrete die tester.

    Abstract translation: 光学对准技术,例如在“倒装芯片”接合中使用的那些技术被用于通过接触构件上的凸起部分与模具建立欧姆接触。 这允许与临时模具夹具精确对准以便测试模具。 然后,所测试的模具可以在已知的良好的模具程序下被认证为具有可接受的可靠度。 这允许在组装之前对模具进行表征,从而可以以未包装的形式转移模具。 欧姆接触优选通过将施加到管芯的压缩力施加到衬底上而形成,从而导致接触构件有限地渗透到接合垫中。 该装置可以用于建立电接触以及使用老化炉和离散模具测试器。

    Method and apparatus for testing an unpackaged semiconductor die
    124.
    发明授权
    Method and apparatus for testing an unpackaged semiconductor die 失效
    用于测试未封装的半导体管芯的方法和装置

    公开(公告)号:US5424652A

    公开(公告)日:1995-06-13

    申请号:US896297

    申请日:1992-06-10

    Abstract: A method and apparatus for testing a singularized semiconductor die prior to packaging the die, thereby allowing for the packaging or other use of only known good die. The apparatus employs a housing of ceramic or other workable material. Contact pads on the interior of the package are coupled to exterior leads with conductive traces. The back side of a semiconductor die to be tested is removably mounted to a lid, and the bond pads on the die are aligned with the contact pads on the interior of the package. The lid is attached to the package thereby electrically coupling the contact pads with the bond pads on the die. Since the package has conventional exterior form and function the package is operational as a functioning device.

    Abstract translation: 一种用于在封装模具之前测试单数化半导体管芯的方法和装置,从而允许包装或仅使用已知的良好管芯。 该装置采用陶瓷或其他可加工材料的壳体。 封装内部的接触焊盘通过导电迹线耦合到外部引线。 要测试的半导体管芯的背面可拆卸地安装到盖上,并且管芯上的接合焊盘与封装内部的接触焊盘对准。 盖子附接到封装,从而将接触垫与模具上的接合焊盘电耦合。 由于包装具有传统的外观形式和功能,因此包装可以作为一个功能性的设备运行。

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