公开(公告)号：US20050054202A1

公开(公告)日：2005-03-10

申请号：US10655972

申请日：2003-09-04

Applicant: Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

Inventor： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

IPC: H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/3105 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76873

Abstract: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

Abstract translation: 一种用于形成铜镶嵌特征的方法，包括提供半导体工艺晶片，其包括形成为延伸穿过至少一个介电绝缘层的厚度的至少一个通孔开口，以及覆盖所述至少一个通孔开口的上覆沟槽开口，以形成双重 大马士革开幕 在所述至少一个通孔开口底部处蚀刻通过蚀刻停止层以暴露下面的铜区域; 在含氢环境中同时加热工艺晶片，进行亚低温DEGAS工艺; 进行原位溅射清洗过程; 并且原位形成阻挡层以使双镶嵌开口成线。

公开(公告)号：US09406500B2

公开(公告)日：2016-08-02

申请号：US13369138

申请日：2012-02-08

Applicant: I-Ting Chen ,  Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： I-Ting Chen ,  Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L21/02041 ,  H01L21/4864 ,  H01L21/67028 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/81911 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A flux residue cleaning system includes first and second immersion chambers, first and second spray chambers, and a drying chamber. The first immersion chamber softens an outer region of a flux residue formed around microbumps interposed between a wafer and a die when the wafer is immersed in a first chemical. The first spray chamber removes the outer region of the flux residue when the wafer is impinged upon by a first chemical spray in order to expose an inner region of the flux residue. The second immersion chamber softens the inner region of the flux residue when the wafer is immersed in a second chemical. The second spray chamber removes the inner region of the flux residue when the wafer is impinged upon by a second chemical spray in order to clean the wafer to a predetermined standard. The drying chamber dries the wafer.

Abstract translation: 助焊剂残渣清洁系统包括第一和第二浸没室，第一和第二喷雾室以及干燥室。 当晶片浸入第一化学品中时，第一浸入室软化在介于晶片和管芯之间的微胶片周围形成的焊剂残余物的外部区域。 当晶片通过第一化学喷雾撞击以暴露焊剂残留物的内部区域时，第一喷雾室除去焊剂残余物的外部区域。 当晶片浸入第二种化学品中时，第二浸入室软化助焊剂残余物的内部区域。 当晶片被第二化学喷雾冲击时，第二喷雾室去除焊剂残余物的内部区域，以便将晶​​片清洁至预定的标准。 干燥室干燥晶片。

公开(公告)号：US09390060B2

公开(公告)日：2016-07-12

申请号：US13420383

申请日：2012-03-14

Applicant: Chien Rhone Wang ,  Chih-Wei Lai ,  Chih-Chiang Chang ,  Kewei Zuo ,  Jing-Cheng Lin

Inventor： Chien Rhone Wang ,  Chih-Wei Lai ,  Chih-Chiang Chang ,  Kewei Zuo ,  Jing-Cheng Lin

IPC: H01L21/66 ,  G06F17/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: G06F17/00 ,  H01L22/12 ,  H01L22/20 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Packaging methods, material dispensing methods and apparatuses, and automatic measurement systems are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a second die to a top surface of a first die, dispensing a first amount of underfill material between the first die and the second die, and capturing an image of the underfill material. Based on the image captured, a second amount or no additional amount of underfill material is dispensed between the first die and the second die.

Abstract translation: 公开了包装方法，材料分配方法和装置以及自动测量系统。 在一个实施例中，包装半导体器件的方法包括将第二管芯耦合到第一管芯的顶表面，在第一管芯和第二管芯之间分配第一量的底部填充材料，以及捕获底部填充材料的图像。 基于所捕获的图像，在第一模具和第二模具之间分配第二量或不需要额外量的底部填充材料。

公开(公告)号：US09299594B2

公开(公告)日：2016-03-29

申请号：US12844113

申请日：2010-07-27

Applicant: Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

Inventor： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

IPC: H01L21/67 ,  H01L21/683 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/6835 ,  H01L21/67092 ,  H01L21/67109 ,  H01L21/6836 ,  H01L22/12 ,  H01L22/26 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The embodiments described provide apparatus and methods for bonding wafers to carriers with the surface contours of plates facing the substrates or carriers are modified either by re-shaping, by using height adjusters, by adding shim(s), or by zoned temperature control. The modified surface contours of such plates compensate the effects that may cause the non-planarity of bonded substrates.

Abstract translation: 所描述的实施例提供了将晶片接合到载体上的装置和方法，其中面向基板或载体的板的表面轮廓通过重新成形，通过使用高度调节器，通过添加垫片或通过分区的温度控制来改变。 这种板的改进的表面轮廓补偿可能导致键合衬底的非平面性的影响。

公开(公告)号：US09245773B2

公开(公告)日：2016-01-26

申请号：US13369126

申请日：2012-02-08

Applicant: Jing-Cheng Lin ,  Szu Wei Lu ,  I-Hsuan Peng

Inventor： Jing-Cheng Lin ,  Szu Wei Lu ,  I-Hsuan Peng

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L23/18 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/17 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1712 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00

Abstract: Semiconductor device packaging methods and structures thereof are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a plurality of second dies to a top surface of a first die, and determining a distance between each of the plurality of second dies and the first die. The method also includes determining an amount of underfill material to dispose between the first die and each of the plurality of second dies based on the determined distance, and disposing the determined amount of the underfill material under each of the plurality of second dies.

Abstract translation: 公开了半导体器件封装方法及其结构。 在一个实施例中，封装半导体器件的方法包括将多个第二管芯耦合到第一管芯的顶表面，以及确定多个第二管芯和第一管芯之间的距离。 该方法还包括基于确定的距离来确定在第一模具和第一模具中的每一个之间配置的底部填充材料的量，以及将确定量的底部填充材料设置在多个第二模具的每一个下。

公开(公告)号：US09000584B2

公开(公告)日：2015-04-07

申请号：US13338820

申请日：2011-12-28

Applicant: Jing-Cheng Lin ,  Jui-Pin Hung ,  Nai-Wei Liu ,  Yi-Chao Mao ,  Wan-Ting Shih ,  Tsan-Hua Tung

Inventor： Jing-Cheng Lin ,  Jui-Pin Hung ,  Nai-Wei Liu ,  Yi-Chao Mao ,  Wan-Ting Shih ,  Tsan-Hua Tung

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.

Abstract translation: 提供了在半导体器件基板上形成模制化合物以使得晶片级封装（WLP）中的扇出结构能够实现的机制。 这些机构涉及覆盖围绕接触垫的绝缘层的表面的部分。 这些机制提高了包装的可靠性和包装过程的过程控制。 这些机理还降低了界面分层的风险，并且在后续处理过程中绝缘层过度消除气泡。 这些机制进一步改善了平面化终点。 通过利用接触焊盘和绝缘层之间的保护层，可以减少铜外扩散，并且还可以提高接触焊盘和绝缘层之间的粘附。

公开(公告)号：US08970035B2

公开(公告)日：2015-03-03

申请号：US13624356

申请日：2012-09-21

Applicant: Jing-Cheng Lin ,  Po-Hao Tsai

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/11 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/06102 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11612 ,  H01L2224/11614 ,  H01L2224/1182 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/14155 ,  H01L2224/14156 ,  H01L2224/14177 ,  H01L2224/14515 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16168 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01108 ,  H01L2224/11 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/00

Abstract: A package structure includes a first substrate bonded to a second substrate by Connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar.

Abstract translation: 封装结构包括通过将第一基板上的金属柱连接到第二基板上的连接器而将第一基板接合到第二基板。 第一金属柱形成在第一衬底的第一区域上并覆盖并电连接到金属焊盘，第二金属柱形成在第一衬底的第二区域中的钝化层上。 在金属柱和第一连接器之间形成第一焊接区域，在第二金属柱和第二连接器之间形成第二焊点区域。 第一金属柱的厚度大于第二金属柱的厚度。

公开(公告)号：US08953336B2

公开(公告)日：2015-02-10

申请号：US13412958

申请日：2012-03-06

Applicant: Chin-Fu Kao ,  Wen-Chih Chiou ,  Jing-Cheng Lin ,  Cheng-Lin Huang ,  Po-Hao Tsai

Inventor： Chin-Fu Kao ,  Wen-Chih Chiou ,  Jing-Cheng Lin ,  Cheng-Lin Huang ,  Po-Hao Tsai

IPC: H05K7/10

CPC classification number: H01L24/14 ,  H01L22/32 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14515 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014

Abstract: A surface metal wiring structure for a substrate includes one or more functional μbumps formed of a first metal and an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps. The surface metal wiring structure also includes a plurality of sacrificial μbumps formed of the first metal that are electrically connected to the electrical test pads, where the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps.

Abstract translation: 用于基板的表面金属布线结构包括由第一金属形成的一个或多个功能性μ凸块和由用于接收电测试探针并电连接到所述一个或多个功能性μ凸起的第二金属形成的电测试垫。 表面金属布线结构还包括由第一金属形成的多个牺牲μ凸块，其电连接到电测试焊盘，其中牺牲μ凸块位于比一个或多个功能性μ凸块更靠近电测试垫的位置。

公开(公告)号：US20140035135A1

公开(公告)日：2014-02-06

申请号：US13572302

申请日：2012-08-10

Applicant: Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/118 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/15788 ,  H01L2924/37001 ,  H01L2924/00

Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

Abstract translation: 用于球栅阵列（BGA）的焊料凸块结构包括在至少一个UBM层上形成的至少一个下凸块金属（UBM）层和焊料凸块。 焊料凸块具有凸块宽度和凸块高度，并且凸块高度比凸块宽度的比值小于1。

公开(公告)号：US20130285244A1

公开(公告)日：2013-10-31

申请号：US13457841

申请日：2012-04-27

Applicant: Yung-Chi Lin ,  Wen-Chih Chiou ,  Yen-Hung Chen ,  Sylvia Lo ,  Jing-Cheng Lin

Inventor： Yung-Chi Lin ,  Wen-Chih Chiou ,  Yen-Hung Chen ,  Sylvia Lo ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L21/283

CPC classification number: H01L21/76898 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05541 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05552

Abstract: A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like.

Abstract translation: 公开了一种用于向TSV提供沉积在TSV的顶表面下方的阻挡层的系统和方法，顶表面具有减小的地形变化。 将底部TSV焊盘沉积到通孔中，然后抛光，使得顶表面在衬底顶表面下方。 然后在通孔中沉积阻挡层，并且沉积在阻挡层上的顶部TSV焊盘。 顶部的TSV屏障垫被抛光，以使顶部TSV焊盘的顶部表面与衬底的高度一致。 阻挡垫可以小于约1微米厚，并且顶部TSV垫可以小于约6微米厚。 阻挡垫可以是来自顶部和底部TSV垫的不同金属，并且可以选自包括钛，钽，钴，镍等的组。