公开(公告)号：US20050275048A1

公开(公告)日：2005-12-15

申请号：US10867352

申请日：2004-06-14

Applicant: Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Kyle Kirby ,  Peter Benson ,  James Wark ,  Alan Wood ,  David Hembree ,  Salman Akram ,  Charles Watkins

Inventor： Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Kyle Kirby ,  Peter Benson ,  James Wark ,  Alan Wood ,  David Hembree ,  Salman Akram ,  Charles Watkins

IPC: H01L21/00 ,  H01L23/02 ,  H01L23/48 ,  H01L27/14 ,  H01L27/146 ,  H01L31/00 ,  H01L31/0203 ,  H01L31/0232

CPC classification number: H01L27/14618 ,  H01L23/481 ,  H01L24/48 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.

Abstract translation: 本文公开了微电子成像器和用于封装微电子成像器的方法。 在一个实施例中，微电子成像单元可以包括微电子管芯，图像传感器，电耦合到图像传感器的集成电路以及电耦合到集成电路的接合焊盘。 导电晶片互连延伸穿过管芯并且与焊盘接触。 互连可以包括完全延伸穿过基底的通道和具有至少部分地设置在通道中的导电填充材料的接合垫。 导电支撑构件由接合垫承载和突出。 图像传感器上的盖连接到支撑构件。

公开(公告)号：US20050194180A1

公开(公告)日：2005-09-08

申请号：US10791195

申请日：2004-03-02

Applicant: Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

Inventor： Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

IPC: G01R1/073 ,  H01L21/66 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01R13/24 ,  H05K3/32 ,  H05K3/40 ,  H05K7/06 ,  H05K7/10

CPC classification number: G01R1/0735 ,  G01R1/07314 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01R12/714 ,  H01R13/24 ,  H01R2201/20 ,  H05K3/326 ,  H05K7/1069 ,  H05K2201/0314 ,  H05K2201/09036 ,  H05K2201/10378 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/05599

Abstract: A compliant contact pin assembly, a contactor card, a testing system and methods for making and testing are provided. A compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material and in another embodiment by compliantly flexible portions of the substrate.

Abstract translation: 提供了兼容的接触针组件，接触器卡，测试系统以及制造和测试方法。 柔性接触销组件包括由衬底的一部分形成的接触针，其中触发销通过柔性耦合结构顺应地保持悬挂在衬底内。 衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。 接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。 在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料并且在另一个实施例中通过柔性柔性部分的基底。

公开(公告)号：US20050101037A1

公开(公告)日：2005-05-12

申请号：US10998269

申请日：2004-11-26

Applicant: Warren Farnworth ,  Alan Wood ,  David Hembree

Inventor： Warren Farnworth ,  Alan Wood ,  David Hembree

IPC: H01L21/48 ,  H01L21/60 ,  H01L21/768 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H01L21/66 ,  G01R31/26

CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/82039 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1005 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/0029 ,  H05K3/0032 ,  H05K2201/09472 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions that are covered with a non-oxidizing metal. The method can be used to fabricate stackable semiconductor packages having integrated circuits in electrical communication with the external contacts. The method can also be used to fabricate interconnects for electrically engaging packages, dice and wafers for testing or for constructing electronic assemblies.

Abstract translation: 一种用于制造半导体部件和互连的方法包括以下步骤：提供诸如半导体管芯的衬底，通过穿过衬底的激光钻孔通孔在衬底的相对侧上形成外部触点，以及在通孔中形成导电构件。 导电构件包括被非氧化金属覆盖的扩大端子部分。 该方法可用于制造具有与外部触点电连通的集成电路的可堆叠半导体封装。 该方法还可用于制造用于电接合封装，裸片和晶片用于测试或构建电子组件的互连。

公开(公告)号：US20050084986A1

公开(公告)日：2005-04-21

申请号：US10983111

申请日：2004-11-05

Applicant: David Hembree ,  Alan Wood

Inventor： David Hembree ,  Alan Wood

IPC: H01L21/66 ,  H01L21/00

CPC classification number: H01L22/20 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2224/05099 ,  H01L2924/013

Abstract: A method for fabricating semiconductor components is performed using a laser scanner and a laser imaging process. A substrate, such as a semiconductor wafer, containing multiple semiconductor components, such as dice or packages, is provided. The components include integrated circuits, and component contacts in electrical communication with the integrated circuits. Initially, the components are tested to identify and locate good components and defective components on the substrate. Using data from the testing step and the laser scanner, patterns of conductors are then formed to either repair the defective components, to electrically isolate the defective components for burn-in, or to form component clusters containing only the good components. Alternately, using data from the testing step and the laser scanner, a matching test board can be fabricated, and used to electrically engage the good components, while the defective components remain isolated.

Abstract translation: 使用激光扫描仪和激光成像处理来执行制造半导体部件的方法。 提供了诸如骰子或包装之类的诸如半导体晶片的衬底，其包含多个半导体元件。 这些部件包括集成电路和与集成电路进行电气通信的部件触点。 最初，对组件进行测试以识别和定位衬底上的良好组件和缺陷组件。 使用来自测试步骤和激光扫描仪的数据，然后形成导体图案，以修复有缺陷的部件，将缺陷部件电隔离以进行老化，或形成仅包含良好部件的组件簇。 或者，使用来自测试步骤和激光扫描仪的数据，可以制造匹配的测试板，并且用于电气接合良好部件，同时有缺陷的部件保持隔离。

公开(公告)号：USD340702S

公开(公告)日：1993-10-26

申请号：US744240

申请日：1991-08-13

Applicant: David Hembree

Designer： David Hembree

公开(公告)号：US20080042247A1

公开(公告)日：2008-02-21

申请号：US11859776

申请日：2007-09-23

Applicant: Alan Wood ,  David Hembree

Inventor： Alan Wood ,  David Hembree

IPC: H01L23/495

CPC classification number: H01L23/02 ,  B33Y70/00 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/49429 ,  H01L2224/78301 ,  H01L2224/85001 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85121 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00015 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.

Abstract translation: 半导体部件包括具有基板接触的半导体基板和与该基板接触部接合的贯通线互连（TWI）。 通线互连（TWI）包括通过基板接触和基板的通孔，连接到基板触点的通孔中的导线和线上的触点。 堆叠的半导体部件包括半导体衬底和堆叠在衬底上并结合到衬底上的通孔互连的第二半导体衬底。 一种用于制造具有通孔布线的半导体部件的方法包括以下步骤：提供具有基板接触的半导体基板，通过基板接触形成通孔，并且部分地穿过基板，将导线放置在通孔中，将导线接合到 衬底接触，然后从第二侧使衬底变薄以暴露线上的接触。 用于制造半导体部件的系统包括被配置为将导线放置在通路中并且在导线和基板接触之间形成接合连接的接合毛细管。

公开(公告)号：US20070241078A1

公开(公告)日：2007-10-18

申请号：US11374750

申请日：2006-03-14

Applicant: David Pratt ,  David Hembree

Inventor： David Pratt ,  David Hembree

IPC: H01B13/00 ,  B44C1/22

CPC classification number: H01L24/94 ,  B23B7/02 ,  B32B3/30 ,  B32B7/02 ,  B32B7/14 ,  B32B37/1292 ,  B32B37/144 ,  H01L21/78 ,  H01L24/83 ,  H01L2924/14 ,  H05K13/00 ,  Y10T156/19 ,  Y10T156/1994 ,  Y10T428/14 ,  Y10T428/24479 ,  Y10T428/24521 ,  Y10T428/24562 ,  Y10T428/24612 ,  Y10T428/24752 ,  Y10T428/24802 ,  Y10T428/24851 ,  Y10T428/24942 ,  H01L2924/00

Abstract: Methods and apparatuses for releasably attaching support members to microfeature workpieces to support members are disclosed herein. In one embodiment, for example, a method for processing a microfeature workpiece including a plurality of microelectronic dies comprises forming discrete blocks of material at a first side of a support member. The blocks are arranged on the support member in a predetermined pattern. The method also includes depositing an adhesive material into gaps between the individual blocks of material and placing a first side of the workpiece in contact with the adhesive material and/or the blocks. The method further includes cutting through a second side of the workpiece to singulate the dies and to expose at least a portion of the adhesive material in the gaps. The method then includes removing at least approximately all the adhesive material from the support member and/or the workpiece with a solvent.

Abstract translation: 本文公开了用于将支撑构件可释放地附接到微型工件以支撑构件的方法和装置。 在一个实施例中，例如，用于处理包括多个微电子管芯的微特征工件的方法包括在支撑构件的第一侧上形成分立的材料块。 块以预定图案布置在支撑构件上。 该方法还包括将粘合剂材料沉积在单个材料块之间的间隙中，并且使工件的第一侧与粘合剂材料和/或块接触。 该方法还包括切割穿过工件的第二侧以对模具进行切割并且使间隙中的粘合剂材料的至少一部分露出。 该方法然后包括用溶剂从支撑构件和/或工件移除至少几乎所有的粘合剂材料。

公开(公告)号：US20070202617A1

公开(公告)日：2007-08-30

申请号：US11743636

申请日：2007-05-02

Applicant: David Hembree

Inventor： David Hembree

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L25/0657 ,  B23K20/004 ,  B23K20/005 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45644 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48455 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/78301 ,  H01L2224/8121 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/85043 ,  H01L2224/85045 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/20751 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/3025 ,  H05K3/4046 ,  H05K2201/10287 ,  H05K2203/049 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49162 ,  Y10T29/49169 ,  Y10T29/53213 ,  H01L2924/20752 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Abstract translation: 用于通过导线互连制造半导体部件的方法包括提供具有电路侧，背面和通孔的基板的步骤。 该方法还包括以下步骤：将导线穿过通孔，在背面的导线上形成接触，在电路侧的导线上形成接合接触，然后将线从接合接触件断开。 通线互连包括通孔中的导线，背侧的触点和电路侧的接合触点。 背面的触点和电路侧的接合触点允许多个部件与相邻部件之间的电连接层叠。 用于执行该方法的系统包括具有通孔的基板和具有接合毛细管的引线接合器，所述接合毛细管被配置为使线穿过通孔，并形成接触和接合接触。 半导体部件可用于形成用于电接合或测试其它半导体部件的芯片级部件，晶片级部件，堆叠部件或互连部件。

公开(公告)号：US20070170350A1

公开(公告)日：2007-07-26

申请号：US11727545

申请日：2007-03-27

Applicant: Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Alan Wood ,  Peter Benson ,  James Wark ,  David Hembree ,  Kyle Kirby ,  Charles Watkins ,  Salman Akram

Inventor： Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Alan Wood ,  Peter Benson ,  James Wark ,  David Hembree ,  Kyle Kirby ,  Charles Watkins ,  Salman Akram

IPC: H01L27/00

CPC classification number: H01L27/00 ,  B33Y80/00 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14683 ,  H01L27/14687 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/00014

Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

公开(公告)号：US20070126091A1

公开(公告)日：2007-06-07

申请号：US11296057

申请日：2005-12-07

Applicant: Alan Wood ,  David Hembree

Inventor： Alan Wood ,  David Hembree

IPC: H01L23/495

CPC classification number: H01L23/02 ,  B33Y70/00 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/49429 ,  H01L2224/78301 ,  H01L2224/85001 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85121 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00015 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.