Abstract:
A multi-layer printed circuit board having interlayer resin insulating layers on both sides of a core substrate, respectively, through holes provided to penetrate the core substrate and filled with resin filler, the interlayer resin insulating layers and conductor circuits provided. The resin filler contains an epoxy resin, a curing agent and 10 to 50% of inorganic particles.
Abstract:
Disclosed are a composite body, a method for producing the composite body and a semiconductor device, the composite body comprising a resin layer and a fine wiring and/or via hole being formed in the resin layer, having high adhesion and high reliability, and being capable of high frequencies. Also disclosed are a resin composition and a resin sheet, both of which can provide such a composite body.The composite body comprises a resin layer and an electroconductive layer, wherein a groove having a maximum width of 1 μm or more and 10 μm or less is on a surface of the resin layer; the electroconductive layer is inside the groove; and a surface of the resin layer being in contact with the electroconductive layer has an arithmetic average roughness (Ra) of 0.05 μm or more and 0.45 μm or less, and/or wherein the resin layer has a via hole having a diameter of 1 μm or more and 25 μm or less; the electroconductive layer is inside the via hole; and a surface of the resin layer of the inside of the via hole has an arithmetic average roughness (Ra) of 0.05 μm or more and 0.45 μm or less. The resin composition comprises an inorganic filler and a thermosetting resin, wherein the inorganic filler contains coarse particles having a diameter of more than 2 μm in an amount of 500 ppm or less. The resin sheet comprises a resin layer and a substrate, wherein the resin layer is on the substrate and comprises the resin composition.
Abstract:
A method of manufacturing a wiring board including forming a first wiring board, the forming of the first board including forming a substrate, forming a first insulation layer on a surface of the substrate and a second insulating layer on the opposite surface of the substrate, forming a via in one of the layers, and cutting the first layer in a first area and cutting the second layer in a second area offset from the first area to form a first substrate laminated to a second substrate with the substrate interposed therebetween, the second substrate having a smaller mounting area than that of the first substrate such that the first substrate extends beyond edge of the second substrate, connecting a pliable member to the substrate, and connecting the member to a second wiring board to connect the first and second boards. One or more insulation layers are a non-pliable layer.
Abstract:
The invention relates to a multilayer printed circuit board structure comprising a stack of plurality of electrically insulating and/or electroconductive layers and at least one passive or active electrical component arranged inside the stack of layers, the component extending laterally only in part of the surface extension of the stack of layers. The invention also relates to a passive or active electrical component mounted on the stack, to an associated wiring, and to a corresponding production method. According to the invention, the insert is embedded between two electrically insulating liquid resin layers or prepreg layers extending over the entire surface and covering the insert on both sides, the insert being surrounded by a resin material that is liquefied by compression or lamination of the structure. The invention structure can be used in printed circuit board technology.
Abstract:
An electronic component capable of effectively dissipating heat generated in an LED chip and other elements is provided. A light emitting unit 1 includes a substrate 2 made of copper or aluminum, an insulating layer 3 formed on the surface thereof, a circuit pattern 4 formed on the insulating layer 3, and a circuit pattern 5 formed on the substrate 2 through an opening 3a that has been formed in advance in the insulation layer 3. An LED chip 6 is mounted on the circuit patterns 4 and 5 by using solder 7. The LED chip 6 includes a ceramic substrate 9, electrodes 10 and 11 formed thereon, and an LED die 12 as a light emitting portion disposed on the electrode 11, which is one of the electrodes. Terminals 13 and 14 are provided on the upper surface of the LED die 12. The terminal 13, which is one of the terminals, is connected to the electrode 10 via a bonding wire 15, and the terminal 14, which is the other one of the terminals, is connected to the electrode 11 via a bonding wire 16.
Abstract:
A circuit board may include hybrid via structures configured to connect to components, such as connectors and electronic components, mounted on the circuit board. A hybrid via structure may include one or more micro-vias configured to provide an electrical connection to a signal trace in the circuit board and one or more through-vias configured to provide a ground connection to at least one reference plane in the circuit board. In one embodiment, a plurality of circuit boards including the hybrid via structures and signal traces may be connected to establish a channel supporting differential signaling and data transfer rates of at least about 5 Gb/s. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
Abstract:
A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.
Abstract:
In a wiring substrate in which plural wiring layers and insulating layers are alternately stacked and the adjacent wiring layers are electrically connected through a via hole formed in the insulating layer, plural holes constructing substrate management information recognizable as a character, a symbol, etc. are formed in the outside insulating layer of the insulating layers.
Abstract:
Through holes 36 are formed to penetrate a core substrate 30 and lower interlayer resin insulating layers 50, and via holes 66 are formed right on the through holes 36, respectively. Due to this, the through holes 36 and the via holes 66 are arranged linearly, thereby making it possible to shorten wiring length and to accelerate signal transmission speed. Also, since the through holes 36 and the via holes 66 to be connected to solder bumps 76 (conductive connection pins 78), respectively, are directly connected to one another, excellent reliability in connection is ensured.
Abstract:
A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic. With this structure, the static capacitance of the layered capacitor portion 40 can be high, and an adequate decoupling effect is exhibited even under circumstances in which instantaneous potential drops occur readily.