公开(公告)号：US08106310B2

公开(公告)日：2012-01-31

申请号：US12560208

申请日：2009-09-15

Applicant: Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

Inventor： Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/382 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0796 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board having interlayer resin insulating layers on both sides of a core substrate, respectively, through holes provided to penetrate the core substrate and filled with resin filler, the interlayer resin insulating layers and conductor circuits provided. The resin filler contains an epoxy resin, a curing agent and 10 to 50% of inorganic particles.

Abstract translation: 分别在芯基板两侧分别具有穿透芯基板并填充有树脂填料的通孔的层间树脂绝缘层，层间树脂绝缘层和导体电路的多层印刷电路板。 树脂填料含有环氧树脂，固化剂和10〜50％的无机粒子。

公开(公告)号：US20110308848A1

公开(公告)日：2011-12-22

申请号：US13148774

申请日：2010-02-08

Applicant: Yuka Ito ,  Kenichi Kaneda ,  Yasuaki Mitsui ,  Iji Onozuka ,  Noriyuki Ohigashi ,  Hideki Hara

Inventor： Yuka Ito ,  Kenichi Kaneda ,  Yasuaki Mitsui ,  Iji Onozuka ,  Noriyuki Ohigashi ,  Hideki Hara

IPC: H05K1/18 ,  H05K3/00 ,  B32B3/00

CPC classification number: H05K3/045 ,  H05K3/107 ,  H05K3/281 ,  H05K3/421 ,  H05K3/465 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09563 ,  Y10T29/49124 ,  Y10T428/24355

Abstract: Disclosed are a composite body, a method for producing the composite body and a semiconductor device, the composite body comprising a resin layer and a fine wiring and/or via hole being formed in the resin layer, having high adhesion and high reliability, and being capable of high frequencies. Also disclosed are a resin composition and a resin sheet, both of which can provide such a composite body.The composite body comprises a resin layer and an electroconductive layer, wherein a groove having a maximum width of 1 μm or more and 10 μm or less is on a surface of the resin layer; the electroconductive layer is inside the groove; and a surface of the resin layer being in contact with the electroconductive layer has an arithmetic average roughness (Ra) of 0.05 μm or more and 0.45 μm or less, and/or wherein the resin layer has a via hole having a diameter of 1 μm or more and 25 μm or less; the electroconductive layer is inside the via hole; and a surface of the resin layer of the inside of the via hole has an arithmetic average roughness (Ra) of 0.05 μm or more and 0.45 μm or less. The resin composition comprises an inorganic filler and a thermosetting resin, wherein the inorganic filler contains coarse particles having a diameter of more than 2 μm in an amount of 500 ppm or less. The resin sheet comprises a resin layer and a substrate, wherein the resin layer is on the substrate and comprises the resin composition.

Abstract translation: 公开了一种复合体，该复合体的制造方法以及半导体装置，该复合体包括树脂层和在该树脂层中形成的精细布线和/或通孔，具有高粘合性和高可靠性，并且 能够高频率。 还公开了树脂组合物和树脂片，两者都可以提供这种复合体。 复合体包括树脂层和导电层，其中在树脂层的表面上具有最大宽度为1μm以上且10μm以下的槽; 导电层在槽内; 并且与导电层接触的树脂层的表面的算术平均粗糙度（Ra）为0.05μm以上且0.45μm以下，和/或其中树脂层具有直径为1μm的通孔 以上且25μm以下; 导电层在通孔内; 通孔内侧的树脂层的表面的算术平均粗糙度（Ra）为0.05μm以上且0.45μm以下。 树脂组合物包含无机填料和热固性树脂，其中无机填料含有直径大于2μm的粗颗粒的量在500ppm以下。 树脂片包括树脂层和基材，其中树脂层在基材上并包含树脂组合物。

公开(公告)号：US20110296679A1

公开(公告)日：2011-12-08

申请号：US13215653

申请日：2011-08-23

Applicant: Michimasa TAKAHASHI ,  Masakazu Aoyama

Inventor： Michimasa TAKAHASHI ,  Masakazu Aoyama

IPC: H05K3/36

CPC classification number: H05K3/4691 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00014 ,  H05K1/0366 ,  H05K1/148 ,  H05K3/0052 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method of manufacturing a wiring board including forming a first wiring board, the forming of the first board including forming a substrate, forming a first insulation layer on a surface of the substrate and a second insulating layer on the opposite surface of the substrate, forming a via in one of the layers, and cutting the first layer in a first area and cutting the second layer in a second area offset from the first area to form a first substrate laminated to a second substrate with the substrate interposed therebetween, the second substrate having a smaller mounting area than that of the first substrate such that the first substrate extends beyond edge of the second substrate, connecting a pliable member to the substrate, and connecting the member to a second wiring board to connect the first and second boards. One or more insulation layers are a non-pliable layer.

Abstract translation: 一种制造布线板的方法，包括形成第一布线板，第一板的形成包括形成基板，在基板的表面上形成第一绝缘层，在基板的相对表面上形成第二绝缘层，形成 在一个层中的通孔，并且在第一区域中切割第一层，并且在与第一区域偏移的第二区域中切割第二层，以形成层压到第二基板的第一基板，其中介于其间的基板，第二基板 具有比第一基板更小的安装面积，使得第一基板延伸超过第二基板的边缘，将柔性构件连接到基板，并且将构件连接到第二布线板以连接第一和第二板。 一个或多个绝缘层是非柔性层。

公开(公告)号：US08072768B2

公开(公告)日：2011-12-06

申请号：US11988289

申请日：2006-07-04

Applicant: Ulrich Ockenfuss ,  Thomas Gottwald

Inventor： Ulrich Ockenfuss ,  Thomas Gottwald

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01L2224/16227 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/15192 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/141 ,  H05K3/284 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/049 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2201/2036 ,  Y10T428/24917 ,  H01L2924/00

Abstract: The invention relates to a multilayer printed circuit board structure comprising a stack of plurality of electrically insulating and/or electroconductive layers and at least one passive or active electrical component arranged inside the stack of layers, the component extending laterally only in part of the surface extension of the stack of layers. The invention also relates to a passive or active electrical component mounted on the stack, to an associated wiring, and to a corresponding production method. According to the invention, the insert is embedded between two electrically insulating liquid resin layers or prepreg layers extending over the entire surface and covering the insert on both sides, the insert being surrounded by a resin material that is liquefied by compression or lamination of the structure. The invention structure can be used in printed circuit board technology.

Abstract translation: 本发明涉及一种多层印刷电路板结构，其包括多个电绝缘和/或导电层的堆叠以及布置在层叠层内的至少一个无源或有源电气元件，所述元件横向延伸仅部分表面延伸部分 的堆叠层。 本发明还涉及安装在堆叠上的无源或有源电气部件，相关布线以及相应的制造方法。 根据本发明，插入物嵌入两个在整个表面上延伸并且在两侧覆盖插入物的电绝缘液体树脂层或预浸料层之间，插入物由树脂材料包围，该树脂材料通过压缩或层压结构液化 。 本发明的结构可用于印刷电路板技术。

公开(公告)号：US08044341B2

公开(公告)日：2011-10-25

申请号：US12384833

申请日：2009-04-09

Applicant: Tomihisa Saito

Inventor： Tomihisa Saito

IPC: H01J40/14

CPC classification number: H05K1/0203 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05K1/05 ,  H05K3/3442 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/10106 ,  H01L2924/00014

Abstract: An electronic component capable of effectively dissipating heat generated in an LED chip and other elements is provided. A light emitting unit 1 includes a substrate 2 made of copper or aluminum, an insulating layer 3 formed on the surface thereof, a circuit pattern 4 formed on the insulating layer 3, and a circuit pattern 5 formed on the substrate 2 through an opening 3a that has been formed in advance in the insulation layer 3. An LED chip 6 is mounted on the circuit patterns 4 and 5 by using solder 7. The LED chip 6 includes a ceramic substrate 9, electrodes 10 and 11 formed thereon, and an LED die 12 as a light emitting portion disposed on the electrode 11, which is one of the electrodes. Terminals 13 and 14 are provided on the upper surface of the LED die 12. The terminal 13, which is one of the terminals, is connected to the electrode 10 via a bonding wire 15, and the terminal 14, which is the other one of the terminals, is connected to the electrode 11 via a bonding wire 16.

Abstract translation: 提供能够有效地散发在LED芯片和其他元件中产生的热的电子部件。 发光单元1包括由铜或铝制成的基板2，形成在其表面上的绝缘层3，形成在绝缘层3上的电路图案4和通过开口3a形成在基板2上的电路图案5 预先形成在绝缘层3中。通过使用焊料7将LED芯片6安装在电路图案4,5上.LED芯片6包括陶瓷基板9，形成在其上的电极10和11以及LED 管芯12作为发光部分，设置在作为电极之一的电极11上。 端子13和14设置在LED管芯12的上表面上。作为端子之一的端子13通过接合线15连接到电极10，端子14是另一个 端子经由接合线16连接到电极11。

公开(公告)号：US08044305B2

公开(公告)日：2011-10-25

申请号：US11443763

申请日：2006-05-31

Applicant: Xingjian Cai ,  Ke Wang ,  Qing-lun Chen

Inventor： Xingjian Cai ,  Ke Wang ,  Qing-lun Chen

IPC: H05K1/16

CPC classification number: H05K1/115 ,  H05K1/0237 ,  H05K1/0245 ,  H05K1/112 ,  H05K3/3415 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/09709 ,  H05K2201/10189 ,  H05K2201/10659 ,  Y02P70/613

Abstract: A circuit board may include hybrid via structures configured to connect to components, such as connectors and electronic components, mounted on the circuit board. A hybrid via structure may include one or more micro-vias configured to provide an electrical connection to a signal trace in the circuit board and one or more through-vias configured to provide a ground connection to at least one reference plane in the circuit board. In one embodiment, a plurality of circuit boards including the hybrid via structures and signal traces may be connected to establish a channel supporting differential signaling and data transfer rates of at least about 5 Gb/s. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract translation: 电路板可以包括被配置为连接到安装在电路板上的诸如连接器和电子部件的组件的混合通孔结构。 混合通孔结构可以包括一个或多个微通孔，其被配置为提供与电路板中的信号迹线的电连接以及被配置为提供到电路板中的至少一个参考平面的接地连接的一个或多个通孔。 在一个实施例中，可以连接包括混合通路结构和信号迹线的多个电路板，以建立支持至少约5Gb / s的差分信令和数据传输速率的信道。 当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20110253439A1

公开(公告)日：2011-10-20

申请号：US12818398

申请日：2010-06-18

Applicant: Tzu-Wei Huang

Inventor： Tzu-Wei Huang

IPC: H05K1/11 ,  H05K1/00 ,  H05K3/46 ,  B32B38/10 ,  B23K31/02

CPC classification number: H05K3/4682 ,  B23K11/11 ,  B23K2101/42 ,  B32B37/0084 ,  B32B37/02 ,  B32B37/04 ,  B32B38/04 ,  B32B38/10 ,  B32B2038/047 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2311/00 ,  B32B2311/12 ,  B32B2457/00 ,  B32B2457/08 ,  H05K1/115 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/02 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/46 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/09918 ,  H05K2203/1536 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.

Abstract translation: 电路基板的制造方法包括以下步骤。 两个金属层的周边结合形成密封区域。 在两个金属层上形成两个绝缘层。 在两个绝缘层上形成包括上，下导电层的两个。 然后，将两个绝缘层和两个导电层层叠，使得彼此接合的两个金属层嵌入在两个绝缘层之间。 去除两个绝缘层的一部分和两个导电层的一部分以形成暴露两个金属层的多个盲孔。 在盲孔和剩余的两个导电层上形成导电材料。 两个金属层的密封区域被分离以形成两个分开的电路基板。

公开(公告)号：US08035033B2

公开(公告)日：2011-10-11

申请号：US12372158

申请日：2009-02-17

Applicant: Kazutaka Kobayashi

Inventor： Kazutaka Kobayashi

IPC: H05K1/00

CPC classification number: H05K1/0266 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K1/114 ,  H05K3/244 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09609 ,  H05K2201/09936 ,  Y10T29/49155 ,  H01L2924/00

Abstract: In a wiring substrate in which plural wiring layers and insulating layers are alternately stacked and the adjacent wiring layers are electrically connected through a via hole formed in the insulating layer, plural holes constructing substrate management information recognizable as a character, a symbol, etc. are formed in the outside insulating layer of the insulating layers.

Abstract translation: 在多个布线层和绝缘层交替层叠并且相邻布线层通过形成在绝缘层中的通孔电连接的布线基板中，构成可识别为字符，符号等的基板管理信息的多个孔是 形成在绝缘层的外部绝缘层中。

公开(公告)号：US07999194B2

公开(公告)日：2011-08-16

申请号：US12179201

申请日：2008-07-24

Applicant: Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

Inventor： Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/382 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0796 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Through holes 36 are formed to penetrate a core substrate 30 and lower interlayer resin insulating layers 50, and via holes 66 are formed right on the through holes 36, respectively. Due to this, the through holes 36 and the via holes 66 are arranged linearly, thereby making it possible to shorten wiring length and to accelerate signal transmission speed. Also, since the through holes 36 and the via holes 66 to be connected to solder bumps 76 (conductive connection pins 78), respectively, are directly connected to one another, excellent reliability in connection is ensured.

Abstract translation: 通孔36形成为穿透芯基板30和下层层间树脂绝缘层50，并且通孔66分别形成在通孔36上。 由此，通孔36和通路孔66线性配置，能够缩短布线长度，加速信号传输速度。 此外，由于分别连接到焊料凸块76（导电连接销78）的通孔36和通孔66彼此直接连接，所以确保了良好的连接可靠性。

公开(公告)号：US07982139B2

公开(公告)日：2011-07-19

申请号：US11356350

申请日：2006-02-17

Applicant: Takashi Kariya ,  Akira Mochida

Inventor： Takashi Kariya ,  Akira Mochida

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic. With this structure, the static capacitance of the layered capacitor portion 40 can be high, and an adequate decoupling effect is exhibited even under circumstances in which instantaneous potential drops occur readily.

Abstract translation: 多层印刷电路板10包括：安装部分60，其顶表面上安装有电连接到布线图案32的半导体元件; 以及具有由陶瓷形成的高介电常数层43的电容器部分40和夹在高介电常数层43上的第一和第二层电极41和42。第一和第二层电极41和42中的一个连接到 半导体元件的电源线和第一和第二层电极41和42中的另一个连接到接地线。 在这种多层印刷电路板10中，连接在电源线和接地线之间的层状电容器部分40中包括的高介电常数层43由陶瓷形成。 利用这种结构，层状电容器部分40的静态电容可以很高，并且即使在容易发生瞬时电位下降的情况下也可以发挥足够的去耦效应。