公开(公告)号：US20050287783A1

公开(公告)日：2005-12-29

申请号：US10879838

申请日：2004-06-29

Applicant: Kyle Kirby ,  Salman Akram ,  David Hembree ,  Sidney Rigg ,  Warren Farnworth ,  William Hiatt

Inventor： Kyle Kirby ,  Salman Akram ,  David Hembree ,  Sidney Rigg ,  Warren Farnworth ,  William Hiatt

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/03 ,  H05K3/40 ,  H05K3/42

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

Abstract translation: 本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。 在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。 衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。 该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。 该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。 该方法然后包括用导电材料填充通道。

公开(公告)号：US20050230810A1

公开(公告)日：2005-10-20

申请号：US11151928

申请日：2005-06-14

Applicant: Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

Inventor： Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

IPC: G01R1/073 ,  H01L21/66 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01R13/24 ,  H05K3/32 ,  H05K3/40 ,  H05K7/06 ,  H05K7/10

CPC classification number: G01R1/0735 ,  G01R1/07314 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01R12/714 ,  H01R13/24 ,  H01R2201/20 ,  H05K3/326 ,  H05K7/1069 ,  H05K2201/0314 ,  H05K2201/09036 ,  H05K2201/10378 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/05599

Abstract: A compliant contact pin assembly and a contactor card are provided. A compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.

Abstract translation: 提供了柔性接触销组件和接触器卡。 柔性接触销组件包括由衬底的一部分形成的接触针，其中触发销通过柔性耦合结构顺应地保持悬挂在衬底内。 衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。 接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。 在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料，并且在另一个实施例中，通过柔性柔性部分的衬底。

公开(公告)号：US20050229393A1

公开(公告)日：2005-10-20

申请号：US11152496

申请日：2005-06-14

Applicant: Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

Inventor： Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

IPC: G01R1/073 ,  H01L21/66 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01R13/24 ,  H05K3/32 ,  H05K3/40 ,  H05K7/06 ,  H05K7/10

CPC classification number: G01R1/0735 ,  G01R1/07314 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01R12/714 ,  H01R13/24 ,  H01R2201/20 ,  H05K3/326 ,  H05K7/1069 ,  H05K2201/0314 ,  H05K2201/09036 ,  H05K2201/10378 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/05599

Abstract: A compliant contact pin assembly method for making is provided. A compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.

Abstract translation: 提供了一种用于制造的柔性接触销组装方法。 柔性接触销组件包括由衬底的一部分形成的接触针，其中触发销通过柔性耦合结构顺应地保持悬挂在衬底内。 衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。 接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。 在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料，并且在另一个实施例中，通过柔性柔性部分的衬底。

公开(公告)号：US20050191876A1

公开(公告)日：2005-09-01

申请号：US11122626

申请日：2005-05-05

Applicant: David Hembree ,  Salman Akram ,  Derek Gochnour

Inventor： David Hembree ,  Salman Akram ,  Derek Gochnour

IPC: G01R1/04 ,  H01R12/00

CPC classification number: G01R1/0466 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49153 ,  Y10T29/53209 ,  Y10T29/5323

Abstract: A spring element used in a temporary package for testing semiconductors is provided. The spring element is compressed so as to press the semiconductor, either in the form of a bare semiconductor die or as part of a package, against an interconnect structure. The spring element is configured so that it provides sufficient pressure to keep the contacts on the semiconductor in electrical contact with the interconnect structure. Material is added and/or removed from the spring element so that it has the desired modulus of elasticity. The shape of the spring element may also be varied to change the modulus of elasticity, the spring constant, and the force transfer capabilities of the spring element.

Abstract translation: 提供了用于测试半导体的临时封装中的弹簧元件。 弹簧元件被压缩以将半导体以裸半导体管芯的形式或作为封装的一部分压在互连结构上。 弹簧元件构造成使得其提供足够的压力以保持半导体上的触点与互连结构电接触。 向弹簧元件添加和/或移除材料，使其具有所需的弹性模量。 弹簧元件的形状也可以改变以改变弹性元件的弹性模量，弹簧常数和力传递能力。

公开(公告)号：US20050093558A1

公开(公告)日：2005-05-05

申请号：US10999202

申请日：2004-11-29

Applicant: David Hembree

Inventor： David Hembree

IPC: G01R1/04 ,  G01R3/00 ,  H05K1/11 ,  H05K3/32 ,  G01R31/02

CPC classification number: H05K3/325 ,  G01R1/0483 ,  G01R3/00 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/4824 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H05K1/112 ,  H01L2924/00014

Abstract: A test carrier for testing bumped semiconductor components such dice, chip scale packages, BGA devices, and wafers is provided. The test carrier includes a base for retaining one or more components and contact members for making temporary electrical connections with contact balls on the components (e.g., solder balls). The test carrier also includes terminal contacts formed as hard metal balls, as hard metal balls coated with a non-oxidizing metal layer, or as glass, ceramic or plastic members coated with a conductive material. The contact members on the base protect the contact balls on the components from deformation during testing and handling. The terminal contacts on the test carrier are configured for multiple uses in a production environment without deformation. Also provided is a calibration carrier for calibrating semiconductor test systems for bumped components, and a cleaning carrier for cleaning test sockets for bumped components. The calibration carrier can include on board evaluation circuitry for evaluating electrical characteristics of a test system, such as contact resistances between electrical connectors of a test socket and terminal contacts on the calibration carrier. The cleaning carrier includes terminal contacts formed of a solder wettable material configured to attract solder contaminants in test sockets.

公开(公告)号：US20050007133A1

公开(公告)日：2005-01-13

申请号：US10911119

申请日：2004-08-03

Applicant: David Hembree

Inventor： David Hembree

IPC: H01L21/00 ,  B25J15/02

CPC classification number: H01L21/67253 ,  H01L21/67248

Abstract: The present invention includes an electronic device workpiece processing apparatus and method of communicating signals within an electronic device workpiece processing apparatus. One embodiment of s an electronic device workpiece processing apparatus includes a chuck including a surface, an electrical coupling adjacent the surface, and electrical interconnect configured to connect with the electrical coupling of the chuck and conduct a signal within the chuck; an intermediate member having a first surface and a second surface and the intermediate member including: an electrical coupling adjacent the first surface and configured to couple with the electrical coupling of the chuck; an electrical coupling adjacent the second surface; and an electrical interconnect configured to connect the electrical coupling adjacent the first surface and the electrical coupling adjacent the second surface; and an electronic device workpiece configured to couple with the second surface of the intermediate member, the electronic device workpiece including a sensor and an electrical coupling configured to provide electrical connection of the sensor with the electrical coupling of the second surface of the intermediate member.

Abstract translation: 本发明包括电子装置工件处理装置和在电子装置工件处理装置内传送信号的方法。 电子设备工件处理设备的一个实施例包括：卡盘，其包括表面，邻近表面的电耦合;以及被配置为与卡盘的电耦合连接并在卡盘内传导信号的电互连; 中间构件，具有第一表面和第二表面，并且所述中间构件包括：与所述第一表面相邻并且被配置为与所述卡盘的电耦合耦合的电耦合; 邻近第二表面的电耦合; 以及电互连，其被配置为将邻近所述第一表面的所述电耦合和邻近所述第二表面的所述电耦合连接; 以及电子设备工件，被配置为与所述中间构件的第二表面联接，所述电子设备工件包括传感器和电耦合，所述电耦合被配置为提供所述传感器与所述中间构件的第二表面的电耦合的电连接。

公开(公告)号：US5559444A

公开(公告)日：1996-09-24

申请号：US452990

申请日：1995-05-30

Applicant: Warren Farnworth ,  Salman Akram ,  David Hembree

Inventor： Warren Farnworth ,  Salman Akram ,  David Hembree

IPC: G01R1/04 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  G01R1/02

CPC classification number: G01R1/0466 ,  G01R1/0483 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/80 ,  H05K3/4007 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2863 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423 ,  Y10T29/49155

Abstract: A method and apparatus for testing unpackaged semiconductor dice is provided. The method includes forming an interconnect-alignment fixture for use in a test apparatus adapted to hold and apply test signals to the die during burn-in and full functionality testing. The interconnect-alignment fixture includes an interconnect plate formed out of a material such as silicon. The interconnect plate includes raised contact members covered with a conductive layer and adapted to penetrate contact locations on the die to a limited penetration depth. The interconnect-alignment fixture also includes an alignment plate formed with etched alignment openings for aligning contact locations on the die with the contact members on the interconnect plate during the test procedure. In addition, the alignment plate includes access openings for establishing an electrical connection to the contact members on the interconnect plate using wire bonding or mechanical electrical connectors. The interconnect plate and alignment plate are fabricated at the wafer level and then singulated using semiconductor circuit fabrication techniques.

Abstract translation: 提供了一种用于测试未封装的半导体晶片的方法和装置。 该方法包括形成用于测试装置中的互连对准夹具，其适于在老化和全功能测试期间保持并施加测试信号至模具。 互连对准夹具包括由诸如硅的材料形成的互连板。 互连板包括覆盖有导电层的凸起的接触构件，并且适于将模具上的接触位置穿透到有限的穿透深度。 互连对准夹具还包括形成有蚀刻对准开口的对准板，用于在测试过程期间将模具上的接触位置与互连板上的接触构件对准。 此外，对准板包括进入开口，用于使用引线接合或机械电连接器建立与互连板上的接触构件的电连接。 互连板和对准板在晶片级制造，然后使用半导体电路制造技术进行分割。

公开(公告)号：US20070246819A1

公开(公告)日：2007-10-25

申请号：US11409638

申请日：2006-04-24

Applicant: David Hembree ,  Alan Wood

Inventor： David Hembree ,  Alan Wood

IPC: H01L23/04

CPC classification number: H01L24/16 ,  G01R1/06716 ,  G01R1/07307 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02125 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/0333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/45116 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45655 ,  H01L2224/45684 ,  H01L2224/45698 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48455 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/4899 ,  H01L2224/48992 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/10155 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45164 ,  H01L2924/013 ,  H01L2924/00013

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked-systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Abstract translation: 半导体部件包括具有衬底接触的半导体衬底和附着到衬底触点的通线互连（TWI）。 通线互连提供了在半导体衬底的相对的第一和第二侧上具有触点的多电平互连。 通线互连（TWI）包括穿过基板触点和基板的通孔，通孔中的导线与基板接触具有接合连接，接近第一侧的导线上的第一触点和第二触点 电线靠近第二侧。 通线互连（TWI）还包括聚合物层，其部分地封装通孔互连（TWI），同时使第一触点暴露。 半导体组件可用于制造堆叠系统，模块系统和测试系统。 制造半导体部件的方法可以包括用于形成聚合物层的膜辅助成型工艺。

公开(公告)号：US20070200575A1

公开(公告)日：2007-08-30

申请号：US11653066

申请日：2007-01-12

Applicant: David Hembree

Inventor： David Hembree

IPC: G01R31/02

CPC classification number: G01R1/07371 ,  G01R1/07357

Abstract: A contactor card assembly for use with a semiconductor substrate. An upper keeper plate and a lower keeper plate each include a number of conductive pins extending therethrough, situated in vias filled with an elastomeric material and extending beyond the keeper plates to contact a substrate for testing. An intermediate keeper plate is situated between the upper and lower keeper plates and includes conductive pivot bars in channels filled with elastomeric material. Each conductive pin contacts a pivot bar on one side thereof to electrically communicate with a corresponding pin on the opposite side. Under compression, variations in the height of contacts on the substrate under test are adjusted for by the movement of the pins and pivoting of the pivot bar in the elastomeric material. Methods and process for creating the keeper plates and semiconductor and testing assemblies are also included in the present invention.

Abstract translation: 一种与半导体衬底一起使用的接触器卡组件。 上保持板和下保持板各自包括延伸穿过其中的多个导电销，其位于填充有弹性体材料并延伸超过保持板的通孔中以接触用于测试的基板。 中间保持板位于上部和下部保持板之间，并且在通道中包括导电枢转杆，该通道填充有弹性体材料。 每个导电针与其一侧的枢轴接触，以与相对侧上的对应销电连通。 在压缩下，通过销的移动和枢转杆在弹性体材料中的枢转来调节被测衬底上的触点高度的变化。 用于产生保持板，半导体和测试组件的方法和方法也包括在本发明中。

公开(公告)号：US20070200255A1

公开(公告)日：2007-08-30

申请号：US11743689

申请日：2007-05-03

Applicant: David Hembree

Inventor： David Hembree

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/0657 ,  B23K20/004 ,  B23K20/005 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45644 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48455 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/78301 ,  H01L2224/8121 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/85043 ,  H01L2224/85045 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/20751 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/3025 ,  H05K3/4046 ,  H05K2201/10287 ,  H05K2203/049 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49162 ,  Y10T29/49169 ,  Y10T29/53213 ,  H01L2924/20752 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Abstract translation: 用于通过导线互连制造半导体部件的方法包括提供具有电路侧，背面和通孔的基板的步骤。 该方法还包括以下步骤：将导线穿过通孔，在背面的导线上形成接触，在电路侧的导线上形成接合接触，然后将线从接合接触件断开。 通线互连包括通孔中的导线，背侧的触点和电路侧的接合触点。 背面的触点和电路侧的接合触点允许多个部件与相邻部件之间的电连接层叠。 用于执行该方法的系统包括具有通孔的基板和具有接合毛细管的引线接合器，所述接合毛细管被配置为使线穿过通孔，并形成接触和接合接触。 半导体部件可用于形成用于电接合或测试其它半导体部件的芯片级部件，晶片级部件，堆叠部件或互连部件。