公开(公告)号：US09218987B2

公开(公告)日：2015-12-22

申请号：US14173151

申请日：2014-02-05

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Kai Liu ,  François Hébert ,  Lei Shi

IPC分类号： H01L21/56 ,  H01L23/495 ,  H01L23/00 ,  H01L21/50

CPC分类号： H01L21/56 ,  H01L21/50 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.

摘要翻译： 公开了一种具有堆叠互连板的顶侧冷却半导体封装。 半导体封装包括具有端子引线的电路基板，电路基板顶部的半导体管芯，用于将半导体管芯的顶部接触区域与电路基板接合和互连的低热电阻紧密互连板，低热阻堆叠互连板 位于用于顶侧冷却的紧密互连板顶部，用于封装包装的模制密封剂，除了暴露堆叠的互连板的顶表面以保持有效的顶侧冷却。 堆叠的互连板的顶部可以包括在紧密互连板上方的周边突出部。 外围悬垂允许最大化的暴露的顶部表面积用于散热，而不管适用于紧密互连板的其它面积约束。 层叠的互连板可以被部分蚀刻或三维地形成以产生外围悬垂。

公开(公告)号：US09214423B2

公开(公告)日：2015-12-15

申请号：US14174500

申请日：2014-02-06

申请人： Semiconductor Components Industries, LLC

发明人： Ali Salih ,  Chun-Li Liu ,  Gordon M. Grivna

IPC分类号： H01L29/49 ,  H01L23/498 ,  H01L29/66 ,  H01L29/778 ,  H01L21/768 ,  H01L21/78 ,  H01L23/482 ,  H01L29/20 ,  H01L21/683 ,  H01L23/00

CPC分类号： H01L23/5226 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/4824 ,  H01L23/49827 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/84 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2221/68327 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/04034 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/37187 ,  H01L2224/3719 ,  H01L2224/37639 ,  H01L2224/37644 ,  H01L2224/37647 ,  H01L2224/37655 ,  H01L2224/37664 ,  H01L2224/40499 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07811 ,  H01L2224/45099

摘要： In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.

摘要翻译： 在一个实施例中，形成HEMT器件的方法可以包括将导体或多个导体电镀到覆盖在HEMT器件的多个载流电极上的绝缘体上。 该方法还可以包括将连接器附接到导体上或者将多个连接器附接到多个导体上。

公开(公告)号：US09214417B2

公开(公告)日：2015-12-15

申请号：US14186275

申请日：2014-02-21

申请人： Yueh-Se Ho ,  Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu

发明人： Yueh-Se Ho ,  Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu

IPC分类号： H01L23/495 ,  H01L27/088

CPC分类号： H01L23/49575 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L27/088 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

摘要翻译： 组合封装的功率半导体器件包括电连接到管芯焊盘的顶表面的翻转顶部源极低侧MOSFET，第一金属互连板，将高边MOSFET的底部漏极或翻转的高侧MOSFET的顶部源极连接到底部 低端MOSFET的漏极和堆叠在高边MOSFET芯片顶部的第二金属互连板。 高侧，低端MOSFET和IC控制器可以三维封装，减小半导体器件的总体尺寸，并可在相同尺寸的封装内最大化芯片的尺寸，并提高半导体器件的性能。 翻转的低侧MOSFET的顶部源极连接到管芯焊盘的顶表面，并且因此通过裸片的裸露的底表面接地，这简化了裸片焊盘的暴露的底面的形状，并使面积最大化 散热。

公开(公告)号：US20150342074A1

公开(公告)日：2015-11-26

申请号：US14435682

申请日：2013-10-25

申请人： NSK LTD.

发明人： Takashi SUNAGA ,  Noboru KANEKO ,  Osamu MIYOSHI

IPC分类号： H05K7/02

CPC分类号： H05K7/02 ,  H01L23/142 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/291 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/35847 ,  H01L2224/3701 ,  H01L2224/37013 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40227 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/4112 ,  H01L2224/48 ,  H01L2224/73263 ,  H01L2224/77272 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84424 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/85 ,  H01L2224/9221 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/1031 ,  H05K2201/10409 ,  Y02P70/611 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/33 ,  H01L2924/00012 ,  H01L2924/00

摘要： To provide a semiconductor module capable of shortening of the manufacturing tact time, reducing the manufacturing costs, and improving assembility. A semiconductor module (30) includes substrate (31) made of metal, an insulating layer (32) formed on the substrate (31), a plurality of wiring patterns (33a to 33d) formed on the insulating layer (32), a bare-chip transistor (35) mounted on a wiring pattern (33a) via a solder (34a); and a metal plate connector (36a, 36b) jointing an electrode (S, G) of the bare-chip transistor (35) and a wiring pattern (33b, 33c) via a solder (34b, 34c). The metal plate connector (36a, 36b) has a bridge shape, and has a flat surface and a center of gravity at a middle portion of the component.

摘要翻译： 提供能够缩短制造节拍时间，降低制造成本，提高组装性的半导体模块。 半导体模块（30）包括由金属制成的基板（31），形成在基板（31）上的绝缘层（32），形成在绝缘层（32）上的多个布线图案（33a〜33d） 通过焊料（34a）安装在布线图案（33a）上的芯片晶体管（35）; 以及通过焊料（34b，34c）将裸芯片晶体管（35）的电极（S，G）和布线图案（33b，33c）接合的金属板连接器（36a，36b）。 金属板连接器（36a，36b）具有桥接形状，并且在部件的中间部分具有平坦表面和重心。

公开(公告)号：US20150333034A1

公开(公告)日：2015-11-19

申请号：US14708964

申请日：2015-05-11

申请人： Infineon Technologies AG

发明人： Daniel Bolowski ,  Achim Froemelt ,  Christian Kersting ,  Christian Stahlhut

IPC分类号： H01L23/00 ,  B23K1/20 ,  B23K1/00

CPC分类号： B22F1/0074 ,  B23K1/0016 ,  B23K1/203 ,  H01L21/00 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/29026 ,  H01L2224/32225 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83065 ,  H01L2224/83359 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method includes providing a subassembly having a circuit carrier with a first metallic surface portion, a first joining partner, which is integrally connected to the first metallic surface portion by means of a first connecting layer, and a second metallic surface portion. In a heat treatment, the second metallic surface portion is held uninterruptedly at temperatures which are higher than a minimum heat-treatment temperature of at least 300° C. Moreover, a second joining partner is provided. A fixed connection is produced between the second joining partner and the subassembly in that the second joining partner is integrally connected to the subassembly following completion of the heat treatment on the second surface portion.

摘要翻译： 一种方法包括提供具有第一金属表面部分的电路载体的子组件，通过第一连接层与第一金属表面部分一体地连接的第一接合配合体和第二金属表面部分。 在热处理中，第二金属表面部分在高于至少300℃的最小热处理温度的温度下不间断地保持。此外，提供第二接合对象。 在第二接合伙伴和子组件之间产生固定连接，因为在第二表面部分上的热处理完成之后，第二接合伙伴一体地连接到子组件。

公开(公告)号：US20150318233A1

公开(公告)日：2015-11-05

申请号：US14800903

申请日：2015-07-16

申请人： Texas Instruments Incorporated

发明人： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L25/07 ,  H01L23/00 ,  H01L25/16

CPC分类号： H01L23/49575 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/072 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/37599 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1425 ,  H01L2924/1426 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H02M3/155 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2224/05599

摘要： A power supply system has a QFN leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound.

摘要翻译： 电源系统具有带引线和焊盘的QFN引线框架。 面对电路板的焊盘表面具有凹陷的部分，其深度和轮廓适合于并置并联和控制FET半导体芯片。 控制FET的输入端子和同步FET的接地输出端子与焊盘（开关节点端子）的未凹入部分共面，使得所有端子可以直接附接到电路板的触点。 驱动器和控制芯片垂直地堆叠到相对的焊盘表面并且封装在封装复合体中。

公开(公告)号：US09177915B2

公开(公告)日：2015-11-03

申请号：US14133102

申请日：2013-12-18

申请人： PANASONIC CORPORATION

发明人： Kazuhiro Kaibara

IPC分类号： H01L23/485 ,  H01L23/528 ,  H01L23/00 ,  H01L23/482 ,  H01L29/417 ,  H01L23/532 ,  H01L29/812 ,  H01L29/06 ,  H01L29/778 ,  H01L29/20

CPC分类号： H01L23/528 ,  H01L23/4824 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/07 ,  H01L24/08 ,  H01L24/09 ,  H01L24/37 ,  H01L24/45 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/7787 ,  H01L29/812 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05027 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/06181 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48611 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48671 ,  H01L2224/48711 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48771 ,  H01L2224/48811 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48871 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01005 ,  H01L2224/84

摘要： A nitride semiconductor device includes first electrode interconnect layers and second electrode interconnect layers formed over a nitride semiconductor layer, a first insulating film formed on the first and second electrode interconnect layers and including first openings, first interconnect layers and second interconnect layers formed on the first insulating film and respectively connected to the first electrode interconnect layers and the second electrode interconnection layers through the first openings, a second insulating film formed on the first and second interconnect layers and including second openings, and a first pad layer and a second pad layer formed on the second insulating film and respectively connected to the first interconnect layers and the second interconnect layers through the second openings.

摘要翻译： 氮化物半导体器件包括在氮化物半导体层上形成的第一电极互连层和第二电极互连层，形成在第一和第二电极互连层上的第一绝缘膜，并且包括第一开口，第一互连层和第一互连层， 绝缘膜，并且分别通过第一开口连接到第一电极互连层和第二电极互连层，形成在第一和第二互连层上并包括第二开口的第二绝缘膜，以及形成的第一焊盘层和第二焊盘层 并且分别通过第二开口连接到第一互连层和第二互连层。

公开(公告)号：US09171817B2

公开(公告)日：2015-10-27

申请号：US14015726

申请日：2013-08-30

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Takeshi Miyakawa

IPC分类号： H01L23/495 ,  H01L23/00

CPC分类号： H01L24/29 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49527 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/06181 ,  H01L2224/29007 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32245 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40247 ,  H01L2224/40491 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a semiconductor chip having an electrode, a connector having a chip contact surface, an interconnecting portion, and an external electrode terminal contact surface, the chip contact surface being electrically connected to the electrode, and a first connection material disposed between the chip contact surface and the electrode, the first connecting material having a surface area that is greater than a surface area of the chip contact surface.

摘要翻译： 半导体器件包括具有电极的半导体芯片，具有芯片接触表面的连接器，互连部分和外部电极端子接触表面，芯片接触表面电连接到电极，并且第一连接材料设置在 芯片接触表面和电极，第一连接材料具有大于芯片接触表面的表面积的表面积。

公开(公告)号：US09171788B1

公开(公告)日：2015-10-27

申请号：US14502902

申请日：2014-09-30

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ming-Chen Lu ,  Hongtao Gao

IPC分类号： H01L23/495

CPC分类号： H01L23/49562 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/84

摘要： A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.

摘要翻译： 公开了一种制造具有小门夹的半导体封装的方法。 第一和第二半导体芯片，其每一个包括源电极和位于顶表面的栅电极，安装在引线框架的两个相邻的引线框架单元上，使得其上形成有第一芯片的引线框单元旋转180° 相对于其上形成有第二半导体芯片的另一个引线框架单元。 第一和第二夹子组安装在第一和第二半导体芯片上，其中第一夹子组连接到第一芯片的栅极电极，第二芯片的源极电极及其相应的引线，第二夹子组 连接到第二芯片的栅电极，第一芯片的源电极及其相应的引线。

公开(公告)号：US20150294926A1

公开(公告)日：2015-10-15

申请号：US14752295

申请日：2015-06-26

申请人： Infineon Technologies AG

发明人： Ralf Otremba ,  Xaver Schloegel ,  Khai Huat Jeffrey Low ,  Chee Soon Law

IPC分类号： H01L23/495 ,  B81C1/00 ,  H01L23/00

CPC分类号： H01L23/49503 ,  B81C1/00301 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/00 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/84 ,  H01L24/85 ,  H01L24/91 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/37144 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45624 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73213 ,  H01L2224/78301 ,  H01L2224/7865 ,  H01L2224/84801 ,  H01L2224/85045 ,  H01L2224/85099 ,  H01L2224/851 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85801 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2924/01016 ,  H01L2924/01026 ,  H01L2924/01201

摘要： A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element.

摘要翻译： 模块包括具有至少第一端子接触表面和第二端子接触表面的半导体芯片。 由基于Cu的材料制成的第一接合元件附接到第一端子接触表面，并且第二接合元件附接到第二端子接触表面。 第二结合元件由与第一结合元件的材料不同的材料制成，或者由不同于第一粘结元件的类型的粘结元件制成。