公开(公告)号：US09673171B1

公开(公告)日：2017-06-06

申请号：US14226711

申请日：2014-03-26

申请人： HeeJo Chi ,  HeeSoo Lee ,  Omin Kwon

发明人： HeeJo Chi ,  HeeSoo Lee ,  Omin Kwon

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0652 ,  H01L23/16 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83005 ,  H01L2924/00

摘要： An integrated circuit packaging system and method of manufacture thereof includes: providing a semiconductor die having semiconductor die contacts; depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed; applying a conductive layer on the semiconductor die contacts and the insulation layer; and coupling system interconnects to the conductive layer for electrically connecting the semiconductor die to the system interconnects.

公开(公告)号：US20160190054A1

公开(公告)日：2016-06-30

申请号：US14792447

申请日：2015-07-06

申请人： SooSan Park ,  KyuSang Kim ,  YeoChan Ko ,  KeoChang Lee ,  HeeJo Chi ,  HeeSoo Lee

发明人： SooSan Park ,  KyuSang Kim ,  YeoChan Ko ,  KeoChang Lee ,  HeeJo Chi ,  HeeSoo Lee

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/4828 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83104 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15331 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system and method of manufacture of an integrated circuit packaging system includes: a base substrate, the base substrate includes a base terminal; an integrated circuit device on the base substrate; a bottom conductive joint on the base terminal; a conductive ball on the bottom conductive joint, the conductive ball includes a core body; and an interposer over the conductive ball.

摘要翻译： 一种集成电路封装系统的制造方法和制造方法，其特征在于，包括：基底基板，所述基底基板包括基底; 在基底基板上的集成电路器件; 基端子上的底部导电接头; 底部导电接头上的导电球，导电球包括芯体; 以及导电球上的插入件。

公开(公告)号：US09385100B1

公开(公告)日：2016-07-05

申请号：US14659905

申请日：2015-03-17

申请人： Hun Teak Lee ,  YoungChul Kim ,  Hyunll Bae ,  HeeSoo Lee ,  HeeJo Chi

发明人： Hun Teak Lee ,  YoungChul Kim ,  Hyunll Bae ,  HeeSoo Lee ,  HeeJo Chi

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L24/81 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/8149 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

摘要： An integrated circuit packaging system, and a method of manufacture thereof, includes: an embedded trace substrate having bonding sites and traces embedded in a base material, an insulation layer on the traces, the insulation layer having a top surface coplanar with the top surface of the base material; and an integrated circuit die connected to the bonding sites.

摘要翻译： 一种集成电路封装系统及其制造方法，包括：嵌入迹线基板，其具有嵌入基材中的接合位置和迹线，迹线上的绝缘层，绝缘层具有与顶表面共面的顶表面 基材; 以及连接到接合位置的集成电路管芯。

公开(公告)号：US09735113B2

公开(公告)日：2017-08-15

申请号：US12786008

申请日：2010-05-24

申请人： HeeJo Chi ,  NamJu Cho ,  JunWoo Myung

发明人： HeeJo Chi ,  NamJu Cho ,  JunWoo Myung

IPC分类号： H01L25/065 ,  H01L21/60 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/552 ,  H05K1/18 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H05K3/00 ,  H05K3/42

CPC分类号： H01L23/5389 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3672 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45099 ,  H01L2224/4805 ,  H01L2224/48091 ,  H01L2224/481 ,  H01L2224/48105 ,  H01L2224/48158 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81801 ,  H01L2224/82106 ,  H01L2224/8385 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/3512 ,  H05K1/185 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/426 ,  H01L2924/0665 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die.

公开(公告)号：US09397050B2

公开(公告)日：2016-07-19

申请号：US12551270

申请日：2009-08-31

申请人： HanGil Shin ,  HeeJo Chi ,  NamJu Cho

发明人： HanGil Shin ,  HeeJo Chi ,  NamJu Cho

IPC分类号： H01L21/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/03 ,  H01L23/498

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor wafer contains a plurality of semiconductor die. A plurality of bumps is formed on the semiconductor wafer. The bumps are electrically connected to contact pads on an active surface of the die. The bumps can also be pillars or stud bumps. A first encapsulant is deposited over the bumps. The semiconductor wafer is singulated to separate the die by cutting channels partially through the wafer and back grinding the wafer down to the channels. A second encapsulant is deposited over the die. A first interconnect structure is formed over a first surface of the second encapsulant. The first interconnect structure is electrically connected to the bumps. A second interconnect structure is formed over a second surface of the second encapsulant. Secondary semiconductor components can be stacked over the second interconnect structure. A third encapsulant is deposited over the stacked secondary components and second interconnect structure.

摘要翻译： 半导体晶片包含多个半导体管芯。 在半导体晶片上形成多个凸块。 凸块电连接到管芯的有效表面上的接触焊盘。 颠簸也可以是柱子或柱状凸起。 第一密封剂沉积在凸块上。 将半导体晶片单片化以通过部分地通过晶片切割通道并将晶片向下研磨到通道来分离模具。 第二密封剂沉积在模具上。 在第二密封剂的第一表面上形成第一互连结构。 第一互连结构电连接到凸块。 在第二密封剂的第二表面上形成第二互连结构。 次级半导体部件可以堆叠在第二互连结构上。 第三密封剂沉积在堆叠的次级部件和第二互连结构上。

公开(公告)号：US08716065B2

公开(公告)日：2014-05-06

申请号：US13243886

申请日：2011-09-23

申请人： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

发明人： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L23/02 ,  H01L23/31 ,  H01L23/16

CPC分类号： H01L23/49811 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05541 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed.

摘要翻译： 一种制造集成电路封装系统的方法，包括：提供基底; 将基底集成电路附接在基底基板上; 在所述基底基板上和所述基底集成电路周围形成具有基底封装顶侧的基底封装; 形成具有基底通孔头部的基底导电通孔，通过基底封装并附接到与基底集成电路相邻的基底基板，基底通孔头部从底部封装顶侧露出并共面; 在基底封装上安装插入器结构，其中插入器结构连接到基底通孔头; 以及在所述基底封装顶侧上形成上部封装并且部分地围绕所述插入件结构，所述插入器结构的侧面背离所述基底封装暴露。

公开(公告)号：US08710668B2

公开(公告)日：2014-04-29

申请号：US13163150

申请日：2011-06-17

申请人： HyungMin Lee ,  HeeJo Chi ,  YeongIm Park

发明人： HyungMin Lee ,  HeeJo Chi ,  YeongIm Park

IPC分类号： H01L23/12

CPC分类号： H01L23/3135 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate; molding a first encapsulation above the substrate; forming a via through the first encapsulation; mounting an integrated circuit above the substrate and between sides of the first encapsulation; and forming a second encapsulation covering the integrated circuit and the first encapsulation.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供基板; 在基底上模制第一封装; 通过第一封装形成通孔; 在衬底上方和第一封装的侧面之间安装集成电路; 以及形成覆盖所述集成电路和所述第一封装的第二封装。

公开(公告)号：US20120319263A1

公开(公告)日：2012-12-20

申请号：US13162513

申请日：2011-06-16

申请人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin

发明人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin

IPC分类号： H01L25/065 ,  H01L21/98

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18165 ,  H01L2924/19103 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a through hole; mounting an integrated circuit in the through hole, the integrated circuit having an inactive side and a vertical side; connecting a first interconnect in direct contact with the integrated circuit and the substrate; applying a wire-in-film adhesive around and above the integrated circuit leaving a portion of the vertical side and the inactive side exposed and covering a portion of the first interconnect; and mounting a chip above the integrated circuit and in direct contact with the wire-in-film adhesive.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有通孔的基板; 将集成电路安装在通孔中，集成电路具有非活动侧和垂直侧; 连接与集成电路和衬底直接接触的第一互连; 在集成电路周围和上方施加线内胶粘剂，留下垂直侧的一部分和非活动侧暴露并覆盖第一互连的一部分; 并将芯片安装在集成电路上方并与线内胶粘剂直接接触。

公开(公告)号：US20120153467A1

公开(公告)日：2012-06-21

申请号：US13403889

申请日：2012-02-23

申请人： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

发明人： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

IPC分类号： H01L23/498

CPC分类号： H01L21/50 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/19 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012

摘要： A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die.

公开(公告)号：US20110215448A1

公开(公告)日：2011-09-08

申请号：US12716269

申请日：2010-03-02

申请人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin

发明人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/495 ,  H01L23/552 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit package system includes: providing a base package substrate including: forming component contacts on a component side of the base package substrate, forming system contacts on a system side of the base package substrate, and forming a reference voltage circuit between the component contacts and the system contacts; mounting a first integrated circuit die on the component contacts; mounting a lead frame on the first integrated circuit die and coupled to the component contacts; and isolating a conductive shield from the lead frame, the conductive shield coupled to the reference voltage circuit.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供基底封装基板，包括：在所述基底封装基板的元件侧上形成元件触点，在所述基底封装基板的系统侧形成系统触点，以及形成基准电压 组件触点和系统触点之间的电路; 在组件触点上安装第一集成电路管芯; 将引线框架安装在第一集成电路管芯上并耦合到部件触点; 并且将导电屏蔽与引线框架隔离，所述导电屏蔽件耦合到参考电压电路。