Patent search ap:"STATS CHIPPAC Page LTD."

291.

发明申请
Semiconductor Device and Method of Forming Pre-Molded Substrate to Reduce Warpage During Die Molding 有权
Title translation: 半导体器件和预成型基板的形成方法，以减少模压时的翘曲

公开(公告)号：US20130200527A1

公开(公告)日：2013-08-08

申请号：US13769302

申请日：2013-02-16

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeWook Yang , SeungWon Kim , MinJung Kim

IPC: H01L23/28 , H01L23/538

CPC classification number: H01L23/28 , H01L21/561 , H01L23/3128 , H01L23/3135 , H01L23/5384 , H01L23/562 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/131 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2224/81191 , H01L2224/81815 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06548 , H01L2225/06582 , H01L2924/00013 , H01L2924/01322 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2224/81 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2924/00 , H01L2224/83 , H01L2924/00012

Abstract: A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and conductive layer formed over the substrate. A first encapsulant is deposited over the substrate outside a die attach area of the substrate. The first encapsulant surrounds each die attach area over the substrate and the die attach area is devoid of the first encapsulant. A channel connecting adjacent die attach areas is also devoid of the first encapsulant. A first semiconductor die is mounted over the substrate within the die attach area after forming the first encapsulant. A second semiconductor die is mounted over the first die within the die attach area. An underfill material can be deposited under the first and second die. A second encapsulant is deposited over the first and second die and first encapsulant. The first encapsulant reduces warpage of the substrate during die mounting.

Abstract translation: 半导体器件具有衬底，其具有通过衬底形成的多个导电通孔和形成在衬底上的导电层。第一密封剂沉积在衬底的管芯附着区域外部的衬底上。第一密封剂围绕衬底上的每个管芯附着区域，并且管芯附着区域没有第一密封剂。连接相邻管芯附着区域的通道也没有第一密封剂。在形成第一密封剂之后，第一半导体管芯安装在管芯附着区域内的衬底上。第二半导体管芯安装在管芯附着区域内的第一管芯上。可以在第一和第二模具下沉积底部填充材料。第二密封剂沉积在第一和第二管芯和第一密封剂上。第一密封剂在模具安装期间减少基底的翘曲。

292.

发明申请
Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnect Structure on Leadframe 有权
Title translation: 半导体器件和在引线框上的迹线互连结构上形成垂直偏移键的方法

公开(公告)号：US20130154067A1

公开(公告)日：2013-06-20

申请号：US13765594

申请日：2013-02-12

Applicant: Stats ChipPac, Ltd.

Inventor： Reza A. Pagaila , KiYoun Jang , HunTeak Lee

IPC: H01L23/495

CPC classification number: H01L23/4952 , H01L23/3107 , H01L23/49513 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L24/29 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/05001 , H01L2224/05082 , H01L2224/05111 , H01L2224/05155 , H01L2224/05554 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/16225 , H01L2224/2919 , H01L2224/32057 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/48249 , H01L2224/49109 , H01L2224/49171 , H01L2224/73265 , H01L2224/83385 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10161 , H01L2924/10162 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/0665 , H01L2224/45099 , H01L2924/00 , H01L2924/00012

Abstract: A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.

Abstract translation: 半导体器件具有垂直偏移的BOT互连结构。垂直偏移通过引线框架实现，引线框架具有围绕模板的多个引线。在引线指上形成第一导电层。在引线指上形成第二导电层。每个第二导电层定位成与第一导电层相邻，并且每个第一导电层定位成与第二导电层相邻。第二导电层的高度大于第一导电层的高度。第一和第二导电层可以具有并排布置或交错布置。在第一和第二导电层上形成凸起。接合线电连接到凸块。半导体管芯安装在引线框架的管芯上并电连接到接合线和BOT互连结构。

293.

发明申请
Semiconductor Device and Method of Forming Adjacent Channel and Dam Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material 有权
Title translation: 半导体器件及相邻沟道和坝体材料周围形成基板附着区域以控制底部填充材料向外流动的方法

公开(公告)号：US20130147065A1

公开(公告)日：2013-06-13

申请号：US13760187

申请日：2013-02-06

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungHoon Lee , KiYoun Jang , JoonDong Kim

IPC: H01L23/498 , H01L21/50

CPC classification number: H01L23/49811 , H01L21/50 , H01L21/563 , H01L23/13 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L24/16 , H01L24/73 , H01L24/81 , H01L2224/16225 , H01L2224/16235 , H01L2224/26175 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81815 , H01L2224/83051 , H01L2224/83385 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00

Abstract: A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel.

Abstract translation: 半导体器件具有安装到衬底内部的管芯附着区域的倒装芯片或PoP半导体管芯。基板在芯片附着区域周围具有接触焊盘区域以及管芯附着区域和接触焊盘区域之间的流动控制区域。第一通道形成在流动控制区域内的基板的表面中。第一通道围绕芯片附接区域的周边延伸。在流动控制区域内与第一通道相邻地形成第一坝材料。在模具和衬底之间沉积底部填充材料。第一通道和第一坝材料控制底部填充材料的向外流动，以防止多余的底部填充材料覆盖接触垫区域。可以与第一坝材料相邻地形成第二通道。可以在第一通道附近形成第二坝材料。

294.

发明申请
Semiconductor Device and Method of Forming Cavity in Build-Up Interconnect Structure for Short Signal Path Between Die 审中-公开
Title translation: 半导体器件和在模具之间的短信号路径的建立互连结构中形成腔的方法

公开(公告)号：US20130140683A1

公开(公告)日：2013-06-06

申请号：US13726467

申请日：2012-12-24

Applicant: STATS CHIPPAC, LTD.

Inventor： Reza A. Pagaila

IPC: H01L23/522 , H01L23/34 , H01L21/768 , H01L23/552

CPC classification number: H01L23/522 , H01L21/568 , H01L21/768 , H01L23/3128 , H01L23/315 , H01L23/34 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L23/552 , H01L24/16 , H01L24/19 , H01L24/81 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/16145 , H01L2224/16225 , H01L2224/20 , H01L2224/26175 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73209 , H01L2224/73267 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06582 , H01L2924/00011 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19104 , H01L2924/30105 , H01L2924/3025 , H01L2224/82 , H01L2924/00012 , H01L2924/00 , H01L2224/81 , H01L2224/83 , H01L2224/81805

Abstract: In a semiconductor device, a first semiconductor die is mounted with its active surface oriented to a temporary carrier. An encapsulant is deposited over the first semiconductor die and temporary carrier. The temporary carrier is removed to expose a first side of the encapsulant and active surface of the first semiconductor die. A masking layer is formed over the active surface of the first semiconductor die. A first interconnect structure is formed over the first side of the encapsulant. The masking layer blocks formation of the first interconnect structure over the active surface of the first semiconductor die. The masking layer is removed to form a cavity over the active surface of the first semiconductor die. A second semiconductor die is mounted in the cavity. The second semiconductor die is electrically connected to the active surface of the first semiconductor die with a short signal path.

Abstract translation: 在半导体器件中，第一半导体管芯被安装成其有源表面定向到临时载体。密封剂沉积在第一半导体管芯和临时载体上。去除临时载体以暴露第一半导体管芯的密封剂和有源表面的第一侧。在第一半导体管芯的有源表面上形成掩模层。在密封剂的第一侧上形成第一互连结构。掩模层阻止在第一半导体管芯的有效表面上形成第一互连结构。去除掩模层以在第一半导体管芯的有效表面上形成空腔。第二半导体管芯安装在腔中。第二半导体管芯通过短信号路径电连接到第一半导体管芯的有源表面。

295.

发明申请
Semiconductor Device Having Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers 有权
Title translation: 半导体器件在嵌入式和凸起的键合手指上的迹线互连上具有垂直偏移键

公开(公告)号：US20130134586A1

公开(公告)日：2013-05-30

申请号：US13727116

申请日：2012-12-26

Applicant: STATS ChipPAC, Ltd.

Inventor： KiYoun Jang , SungSoo Kim , YongHee Kang

IPC: H01L23/498

CPC classification number: H01L23/49811 , H01L21/4846 , H01L21/6835 , H01L23/498 , H01L23/49827 , H01L24/06 , H01L2221/68359 , H01L2221/68363 , H01L2224/0401 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H05K3/108 , H05K3/205 , H05K3/4007 , H05K2201/0367 , H05K2201/0376 , H05K2201/097 , H05K2201/09736 , H05K2203/049 , H05K2203/1476 , H01L2924/00

Abstract: A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.

Abstract translation: 半导体器件包括衬底，嵌入并凹入到衬底的第一表面中的第一凹陷导电层和设置在第一表面上方的第一凸起导电层。在第一凹陷导电层的上表面和第一凸起导电层的上表面之间存在第一垂直偏移。该器件包括嵌入并凹入到衬底的第二表面中的第二凹陷导电层。基板的第二表面与第一表面相对。该装置包括设置在第二表面下方的第二凸起导电层和设置在第一凹入和凸起导电层上的互连结构和第二凹入和凸起导电层。在第二凹陷导电层的下表面和第二凹陷导电层的下表面之间存在第二垂直偏移。

296.

发明申请
Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die 有权
Title translation: 半导体器件和形成包含堆叠半导体晶片的EWLB封装的方法通过形成在密封剂周围的导电通孔电连接

公开(公告)号：US20130119559A1

公开(公告)日：2013-05-16

申请号：US13732150

申请日：2012-12-31

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho

IPC: H01L21/56 , H01L23/498

CPC classification number: H01L21/56 , H01L21/561 , H01L21/565 , H01L23/3128 , H01L23/49827 , H01L24/19 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16225 , H01L2224/24011 , H01L2224/24105 , H01L2224/24146 , H01L2224/245 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/821 , H01L2224/92244 , H01L2224/94 , H01L2224/96 , H01L2225/1035 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2224/82 , H01L2924/00014 , H01L2924/0105 , H01L2924/01028 , H01L2924/01022 , H01L2224/19 , H01L2924/00 , H01L2224/03

Abstract: A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers.

Abstract translation: 半导体器件具有第一半导体管芯和围绕第一半导体管芯沉积的第一密封剂。在第一半导体管芯和第一密封剂上形成第一绝缘层。第一导电层形成在第一绝缘层之上，并电连接到第一半导体管芯的接触焊盘。第二半导体管芯安装到第一绝缘层和第一导电层。第二密封剂沉积在第二半导体管芯周围。在第二半导体管芯和第二密封剂上形成第二绝缘层。第二导电层形成在第二绝缘层之上并电连接到第二半导体管芯的接触焊盘。多个导电通孔连续地穿过电连接到第一和第二导电层的第一和第二半导体管芯的覆盖区之外的第一和第二密封剂形成。

297.

发明申请
Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe 有权
Title translation: 使用引线框形成半导体管芯的导电柱和散热片的半导体器件和方法

公开(公告)号：US20130105970A1

公开(公告)日：2013-05-02

申请号：US13683946

申请日：2012-11-21

Applicant: STATS ChipPAC, Ltd.

Inventor： HeeJo Chi , NamJu Cho , HanGil Shin

IPC: H01L23/498 , H01L23/34 , H01L21/56

CPC classification number: H01L23/49816 , H01L21/4832 , H01L21/56 , H01L21/561 , H01L23/3128 , H01L23/34 , H01L23/367 , H01L23/4334 , H01L23/49524 , H01L23/49827 , H01L23/5389 , H01L24/16 , H01L24/18 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/97 , H01L25/105 , H01L2224/04105 , H01L2224/05001 , H01L2224/05008 , H01L2224/05026 , H01L2224/05548 , H01L2224/05569 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/24227 , H01L2224/29099 , H01L2224/29186 , H01L2224/2919 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01047 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2224/82 , H01L2224/81 , H01L2224/83 , H01L2924/05432 , H01L2924/00014 , H01L2924/0542 , H01L2924/0503 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155

Abstract: A semiconductor device has a prefabricated multi-die leadframe with a base and integrated raised die paddle and a plurality of bodies extending from the base. A thermal interface layer is formed over a back surface of a semiconductor die or top surface of the raised die paddle. The semiconductor die is mounted over the raised die paddle between the bodies of the leadframe with the TIM disposed between the die and raised die paddle. An encapsulant is deposited over the leadframe and semiconductor die. Vias can be formed in the encapsulant. An interconnect structure is formed over the leadframe, semiconductor die, and encapsulant, including into the vias. The base is removed to separate the bodies from the raised die paddle. The raised die paddle provides heat dissipation for the semiconductor die. The bodies are electrically connected to the interconnect structure. The bodies operate as conductive posts for electrical interconnect.

Abstract translation: 半导体器件具有预制的多管芯引线框架，其具有基底和集成凸起的裸片焊盘以及从基部延伸的多个主体。热界面层形成在半导体管芯的背表面或凸起的管芯焊盘的顶表面上。半导体管芯安装在引线框架的主体之间的凸起的模板上，并且TIM设置在模具和凸起的模板之间。封装剂沉积在引线框架和半导体管芯上。可以在密封剂中形成通孔。在引线框架，半导体管芯和密封剂之上形成互连结构，包括到通孔中。移除基座以将体与凸起模片分离。凸起的芯片为半导体管芯提供散热。主体电连接到互连结构。主体用作电气互连的导电柱。

298.

发明申请
Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process 有权

公开(公告)号：US20130087913A1

公开(公告)日：2013-04-11

申请号：US13691427

申请日：2012-11-30

Applicant: STATS ChipPAC, Ltd.

Inventor： KiYoun Jang , DaeSik Choi , OhHan Kim , DongSoo Moon

IPC: H01L23/498

CPC classification number: H01L21/4853 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/81192 , H01L2224/814 , H01L2224/81411 , H01L2224/81413 , H01L2224/81416 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81815 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2224/05552

Abstract: A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.