Patent search cpc:"H01L2224/08146" Page 5

41.

发明授权
Electronic system having increased coupling by using horizontal and vertical communication channels 有权

公开(公告)号：US09881911B2

公开(公告)日：2018-01-30

申请号：US13801354

申请日：2013-03-13

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani

IPC: H01L23/48 , H01L21/60 , H05K7/20 , H05K1/00 , H01L25/11 , H01L27/02 , H01L21/768 , H01L25/065 , H01L23/31 , H01L23/66 , H01L23/00 , H01L21/683 , H01L25/10 , H05K1/18 , H01L21/66 , H01L21/56 , H01L23/498

CPC classification number: H01L27/0203 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/768 , H01L22/22 , H01L23/3128 , H01L23/48 , H01L23/49833 , H01L23/66 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/09 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/94 , H01L24/95 , H01L25/0657 , H01L25/105 , H01L2221/68304 , H01L2221/68327 , H01L2221/6834 , H01L2223/6677 , H01L2224/0231 , H01L2224/02313 , H01L2224/02319 , H01L2224/02321 , H01L2224/02371 , H01L2224/0401 , H01L2224/04105 , H01L2224/05569 , H01L2224/06187 , H01L2224/08137 , H01L2224/08146 , H01L2224/12105 , H01L2224/13024 , H01L2224/14183 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/2105 , H01L2224/211 , H01L2224/28105 , H01L2224/29024 , H01L2224/30183 , H01L2224/32145 , H01L2224/32227 , H01L2224/45015 , H01L2224/45099 , H01L2224/48 , H01L2224/48091 , H01L2224/48175 , H01L2224/73207 , H01L2224/73215 , H01L2224/73251 , H01L2224/82106 , H01L2224/94 , H01L2224/95 , H01L2225/06531 , H01L2225/06541 , H01L2225/06555 , H01L2225/06565 , H01L2225/06568 , H01L2225/06572 , H01L2225/06596 , H01L2225/1023 , H01L2225/1064 , H01L2225/107 , H01L2924/00014 , H01L2924/12042 , H01L2924/15159 , H01L2924/207 , H05K1/181 , H05K1/189 , H05K2201/10515 , Y02P70/611 , H01L2224/02 , H01L2224/08 , H01L2224/16 , H01L2224/32 , H01L2224/19 , H01L2924/00

Abstract: An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in PCBs coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

42.

发明授权
Method of multi-chip wafer level packaging 有权

公开(公告)号：US09679882B2

公开(公告)日：2017-06-13

申请号：US15013669

申请日：2016-02-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hang Tung , Chun Hui Yu , Chen-Hua Yu , Da-Yuan Shih

IPC: H01L21/00 , H01L25/00 , H01L23/31 , H01L21/56 , H01L23/00 , H01L25/065 , H01L21/48 , H01L21/768 , H01L21/78

CPC classification number: H01L25/50 , H01L21/4882 , H01L21/561 , H01L21/563 , H01L21/76879 , H01L21/78 , H01L23/3114 , H01L24/03 , H01L24/09 , H01L24/11 , H01L24/17 , H01L24/19 , H01L24/24 , H01L24/27 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L2224/02311 , H01L2224/02381 , H01L2224/0346 , H01L2224/0401 , H01L2224/04105 , H01L2224/05572 , H01L2224/08146 , H01L2224/12105 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73217 , H01L2224/73267 , H01L2224/8203 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06548 , H01L2225/06568 , H01L2225/06589 , H01L2924/00014 , H01L2924/01029 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2224/05552 , H01L2224/03

Abstract: A method of multi-chip wafer level packaging comprises attaching a first semiconductor die to a top side of a wafer, forming a first reconfigured wafer by embedding the first semiconductor die into a first photo-sensitive material layer, forming a first group of through assembly vias in the first photo-sensitive material layer, attaching a second semiconductor die to the first photo-sensitive material layer, forming a second photo-sensitive material layer on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer and forming a second group of through assembly vias in the second photo-sensitive material layer.

43.

发明申请
STRUCTURE AND FORMATION METHOD FOR CHIP PACKAGE 审中-公开

公开(公告)号：US20170117253A1

公开(公告)日：2017-04-27

申请号：US14919378

申请日：2015-10-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Hua YU , Ming-Fa CHEN , Sung-Feng YEH

IPC: H01L25/065 , H01L21/66

CPC classification number: H01L25/0657 , H01L21/568 , H01L21/76898 , H01L22/32 , H01L23/147 , H01L23/3114 , H01L23/3135 , H01L23/481 , H01L23/49811 , H01L23/5389 , H01L24/08 , H01L24/09 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/80 , H01L24/82 , H01L24/94 , H01L24/96 , H01L2224/04105 , H01L2224/05571 , H01L2224/08145 , H01L2224/08146 , H01L2224/08225 , H01L2224/09517 , H01L2224/12105 , H01L2224/16227 , H01L2224/24105 , H01L2224/24226 , H01L2224/25 , H01L2224/2518 , H01L2224/73267 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H01L2224/82031 , H01L2224/821 , H01L2224/9222 , H01L2224/92244 , H01L2224/94 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2924/15311 , H01L2924/3511 , H01L2224/80 , H05K3/467 , H01L2224/80001 , H01L2224/82

Abstract: A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.

44.

发明申请
SEMICONDUCTOR DEVICES HAVING HYBRID STACKING STRUCTURES AND METHODS OF FABRICATING THE SAME 审中-公开

公开(公告)号：US20170110445A1

公开(公告)日：2017-04-20

申请号：US15391424

申请日：2016-12-27

Applicant: PIL-KYU KANG , Byung Lyul Park , Taeyeong Kim , Yeun-Sang Park , Dosun Lee , Ho-Jin Lee , Jinho Chun , JU-IL CHOI , Yi Koan Hong

Inventor： PIL-KYU KANG , Byung Lyul Park , Taeyeong Kim , Yeun-Sang Park , Dosun Lee , Ho-Jin Lee , Jinho Chun , JU-IL CHOI , Yi Koan Hong

IPC: H01L25/00 , H01L21/304 , H01L23/48 , H01L25/065 , H01L21/66 , H01L21/768 , H01L23/00

CPC classification number: H01L25/50 , H01L21/304 , H01L21/561 , H01L21/76898 , H01L22/32 , H01L23/3128 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05568 , H01L2224/0557 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/08146 , H01L2224/131 , H01L2224/13124 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/81191 , H01L2224/81193 , H01L2224/9202 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2225/06596 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/81 , H01L2224/11 , H01L2224/03 , H01L2924/00014 , H01L2924/014

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

45.

发明授权
Stacked IC control through the use of homogenous region 有权
Title translation: 堆叠IC控制通过使用均匀区域

公开(公告)号：US09437578B2

公开(公告)日：2016-09-06

申请号：US14316125

申请日：2014-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-I Hsu , Cheng-Ying Ho , Jeng-Shyan Lin , Feng-Chi Hung , Dun-Nian Yaung

IPC: H01L25/065 , H01L23/48 , H01L21/306 , H01L27/146 , H01L25/00 , H01L21/768 , H01L23/00

CPC classification number: H01L25/0657 , H01L21/30604 , H01L21/76801 , H01L21/76802 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L23/5226 , H01L23/53295 , H01L24/03 , H01L24/09 , H01L24/24 , H01L24/80 , H01L24/82 , H01L24/92 , H01L25/50 , H01L27/14632 , H01L27/14634 , H01L27/14636 , H01L27/14687 , H01L27/1469 , H01L2224/08145 , H01L2224/08146 , H01L2224/24147 , H01L2224/80896 , H01L2224/8203 , H01L2224/92 , H01L2225/06541 , H01L2225/06548 , H01L2924/14 , H01L2224/80001 , H01L2224/82

Abstract: A package includes a semiconductor chip. The semiconductor chip includes a substrate, a plurality of dielectric layers underlying the substrate, a dielectric region penetrating through the plurality of dielectric layers, and a metal pad overlapped by the dielectric region. A conductive plug penetrates through the substrate, the dielectric region, and the metal pad.

Abstract translation: 封装包括半导体芯片。半导体芯片包括衬底，在衬底下面的多个电介质层，穿透多个电介质层的电介质区域和与电介质区域重叠的金属焊盘。导电插塞穿过基板，电介质区域和金属焊盘。

46.

发明申请
STACKED MICROELECTRONIC DICE EMBEDDED IN A MICROELECTRONIC SUBSTRATE 审中-公开

公开(公告)号：US20160148920A1

公开(公告)日：2016-05-26

申请号：US15009731

申请日：2016-01-28

Applicant: Intel Corporation

Inventor： Reinhard Mahnkopf , Wolfgang Molzer , Bernd Memmler , Edmund Goetz , Hans-Joachim Barth , Sven Albers , Thorsten Meyer

IPC: H01L25/00 , H01L21/768 , H01L23/00 , H01L21/56

CPC classification number: H01L23/5389 , H01L21/56 , H01L21/563 , H01L21/76898 , H01L23/3121 , H01L23/5226 , H01L23/5384 , H01L23/562 , H01L24/03 , H01L24/81 , H01L25/0657 , H01L25/074 , H01L25/50 , H01L2224/08146 , H01L2224/16148 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06548 , H01L2225/06568 , H01L2924/181 , H01L2924/00012

Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.

47.

发明授权
Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems 有权
Title translation: 三维（3D）集成电路（IC）（3DIC）和相关系统

公开(公告)号：US09343369B2

公开(公告)日：2016-05-17

申请号：US14280731

申请日：2014-05-19

Applicant: QUALCOMM Incorporated

Inventor： Yang Du , Karim Arabi

IPC: H01L23/48 , H01L21/822 , H01L23/528 , H01L23/522 , H01L21/768 , H01L21/50 , H01L27/06

CPC classification number: H01L25/0652 , H01L21/50 , H01L21/76895 , H01L21/8221 , H01L23/5226 , H01L23/528 , H01L24/05 , H01L24/08 , H01L24/80 , H01L24/83 , H01L25/50 , H01L27/0688 , H01L27/0694 , H01L2224/05571 , H01L2224/056 , H01L2224/08146 , H01L2224/08147 , H01L2224/80006 , H01L2224/80896 , H01L2224/83125 , H01L2224/83895 , H01L2224/9202 , H01L2225/06524 , H01L2225/06555 , H01L2225/06593 , H01L2924/00014

Abstract: Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.

Abstract translation: 公开了构造三维集成电路及相关系统的方法。在一个方面，通过在保持基板上产生诸如晶体管的有源元件来构造第一层。在有源元件上方形成互连金属层。在互连金属层内形成金属焊盘。也创建了第二层，并行或顺序。第二层以与第一层大致相同的方式创建，然后被放置在第一层上，使得相应的金属焊盘对准并且被一层结合到另一层。然后释放第二层的保持基板。然后减薄第二层的背面，使得有源元件的背面（例如，晶体管中的栅极的背面）被暴露。如果需要，可以添加另外的层，基本上重复该过程。

48.

发明授权
Bonding structure for stacked semiconductor devices 有权
Title translation: 堆叠半导体器件的接合结构

公开(公告)号：US09230941B2

公开(公告)日：2016-01-05

申请号：US14229114

申请日：2014-03-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Szu-Ying Chen , Dun-Nian Yaung

IPC: H01L23/00 , H01L25/065 , H01L25/00 , H01L23/522 , H01L23/528 , H01L21/768

CPC classification number: H01L25/0657 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/09 , H01L24/80 , H01L24/89 , H01L24/94 , H01L25/50 , H01L27/14621 , H01L27/14627 , H01L27/14634 , H01L27/1464 , H01L27/14685 , H01L27/1469 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/03616 , H01L2224/0382 , H01L2224/05571 , H01L2224/05573 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/08145 , H01L2224/08146 , H01L2224/09515 , H01L2224/09517 , H01L2224/80011 , H01L2224/80012 , H01L2224/80013 , H01L2224/80014 , H01L2224/8034 , H01L2224/80357 , H01L2224/8036 , H01L2224/80894 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H01L2224/94 , H01L2225/06524 , H01L2225/06541 , H01L2924/12036 , H01L2924/12042 , H01L2924/1433 , H01L2924/1461 , H01L2924/206 , H01L2924/2064 , H01L2924/00 , H01L2224/80 , H01L2924/00012 , H01L2924/00014 , H01L2224/80001

Abstract: A semiconductor device, and a method of fabrication, is introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and a first bonding pad, a second bonding pad, and a first via are formed in the recesses. In some embodiment, the first via may have electrical contact with the first bonding pad and may provide an electrical pathway to a first plurality of metallization layers. The first bonding pad and the second bonding pad in the first substrate are aligned to a third bonding pad and the fourth bonding pad in a second substrate and may be bonded using a direct bonding method. A bond between the first bonding pad and the third bonding pad may provide an electrical pathway between devices on the first substrate and devices on the second substrate.

Abstract translation: 引入半导体器件和制造方法。在一个实施例中，在第一衬底上形成一个或多个钝化层。在钝化层中形成凹部，并且在凹部中形成第一接合焊盘，第二接合焊盘和第一通孔。在一些实施例中，第一通孔可以与第一接合焊盘电接触并且可以提供到第一多个金属化层的电路径。第一基板中的第一接合焊盘和第二接合焊盘与第三接合焊盘和第二接合焊盘对准，并且可以使用直接接合方法接合。第一接合焊盘和第三接合焊盘之间的接合可以在第一基板上的设备和第二基板上的设备之间提供电路径。

49.

发明申请
METHOD OF PLANARIZING RECESSES FILLED WITH COPPER 有权
Title translation: 用铜填充的压痕的方法

公开(公告)号：US20150340269A1

公开(公告)日：2015-11-26

申请号：US14706579

申请日：2015-05-07

Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Maurice Rivoire , Viorel Balan

IPC: H01L21/768 , H01L25/065 , H01L23/532 , H01L21/306 , H01L23/522

CPC classification number: H01L23/53238 , H01L21/30625 , H01L21/3212 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76877 , H01L23/5226 , H01L24/00 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2224/03845 , H01L2224/05026 , H01L2224/05147 , H01L2224/05571 , H01L2224/05573 , H01L2224/05666 , H01L2224/0568 , H01L2224/05681 , H01L2224/05686 , H01L2224/08121 , H01L2224/08146 , H01L2224/80895 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2924/00012 , H01L2924/00014

Abstract: A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by: a) chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is set back with respect to the upper surface of the substrate; b) depositing on the exposed surface of the structure a material covering at least the copper at the level of the recesses; and c) chemical-mechanical planarizing of the structure to expose the substrate with the copper remaining buried under the material. Two such structures are then direct bonded to each other with opposite areas of material having a same topology.

Abstract translation: 一种结构包括具有设置有凹部的上表面的基底，并且涂覆有连续阻挡层，该连续阻挡层具有填充至少凹部的连续铜层。该结构通过以下方式平坦化：a）铜的化学机械抛光，这样的抛光相对于阻挡层是选择性的，使得铜保留在凹部中并相对于衬底的上表面回退; b）在所述结构的暴露表面上沉积至少覆盖所述凹部的所述铜层的材料; 以及c）结构的化学机械平面化，以将铜保留在材料下方露出衬底。然后，两个这样的结构通过具有相同拓扑的材料的相对区域彼此直接结合。