公开(公告)号：US09768067B2

公开(公告)日：2017-09-19

申请号：US15364160

申请日：2016-11-29

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu ,  Ying-Nan Wen ,  Shih-Yi Lee ,  Ho-Yin Yiu

IPC: H01L21/768 ,  H01L21/268 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L21/683 ,  H01L21/78 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/263 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L21/2633 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/43 ,  H01L24/45 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0233 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06135 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/432 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

公开(公告)号：US09754918B2

公开(公告)日：2017-09-05

申请号：US14444681

申请日：2014-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Wen-Ching Tsai ,  Sung-Feng Yeh

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L25/065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/19 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/0212 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/18 ,  H01L2224/24146 ,  H01L2224/73267 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/18162 ,  H01L2224/03 ,  H01L2224/80001 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/014

Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.

公开(公告)号：US20170229404A1

公开(公告)日：2017-08-10

申请号：US15495788

申请日：2017-04-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Tsei-Chung Fu

IPC: H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/02068 ,  H01L21/02118 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/32051 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4864 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76888 ,  H01L21/76898 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L33/62 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05005 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/1183 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13101 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/0541 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.

公开(公告)号：US09728514B2

公开(公告)日：2017-08-08

申请号：US15207287

申请日：2016-07-11

Applicant: Amkor Technology, Inc.

Inventor： Jong Sik Paek ,  Won Chul Do ,  Doo Hyun Park ,  Eun Ho Park ,  Sung Jae Oh

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/31 ,  H01L23/367 ,  H01L21/60

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76805 ,  H01L23/3157 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/13006 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/16152 ,  H01L2924/164 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

公开(公告)号：US20170194273A1

公开(公告)日：2017-07-06

申请号：US15156764

申请日：2016-05-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： SHENG-CHAU CHEN ,  SHIH-PEI CHOU ,  MING-JHE LEE ,  KUO-MING WU ,  CHENG-HSIEN CHOU ,  CHENG-YUAN TSAI ,  YEUR-LUEN TU

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/02 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05019 ,  H01L2224/05082 ,  H01L2224/05088 ,  H01L2224/05091 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L21/304 ,  H01L21/76898 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/00012

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

公开(公告)号：US20170190572A1

公开(公告)日：2017-07-06

申请号：US14986189

申请日：2015-12-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo Lung Pan ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Yu-Feng Chen ,  Yu-Jen Cheng

IPC: B81C1/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  B81B7/00 ,  H01L23/48

CPC classification number: B81C1/0023 ,  B81B7/007 ,  B81B2207/012 ,  B81B2207/07 ,  B81C2203/0792 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/08225 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/92244 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: Integrated circuit packages and methods of forming same are provided. A method includes attaching a first die and a second die to a carrier, the first die having a first contact pad, the second die having a second contact pad, the first contact pad and the second contact pad having different structures. A release layer is formed over the first die and the second die. An encapsulant is injected between the carrier and the release layer. One or more redistribution layers (RDLs) are formed over the first die, the second die and the encapsulant, the first contact pad and the second contact pad being in electrical contact with the one or more RDLs.

公开(公告)号：US09698121B2

公开(公告)日：2017-07-04

申请号：US14165280

申请日：2014-01-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chao Mao ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/11013 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of packaging a semiconductor device, comprising: attaching a plurality of dies to a carrier wafer, wherein each of the dies includes a top surface; forming a molding compound layer over the dies, wherein the top surface of the dies are covered by the molding compound layer; removing a first portion of the molding compound layer; removing a second portion of the molding compound layer such that the top surface of the dies is not covered by the molding compound layer; forming a redistribution layer (RDL) over the top surface of the dies; forming a plurality of solder balls over at least a portion of the RDL; and singulating the dies.

公开(公告)号：US09698113B2

公开(公告)日：2017-07-04

申请号：US15221856

申请日：2016-07-28

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

Inventor： Qifeng Wang

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/50 ,  H01J37/32

CPC classification number: H01L24/11 ,  H01J37/32 ,  H01L21/02068 ,  H01L21/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1181 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/81013 ,  H01L2224/81022 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/3841 ,  H01L2924/00014

Abstract: A method for treating a chip packaging structure includes providing a chip packaging structure having at least a first electrical connect structure and a second electrical connect structure, and an insulation layer exposing portions of the first electrical connect structure and the second electrical connect structure; selecting a plasma gas based on materials of the first electrical connect structure and the second electrical connect structure and a type of process forming the first electrical connect structure and the second electrical connect structure, wherein metal cations are left on the insulation layer; performing a plasma treatment process using the selected plasma gas on the first electrical connect structure, the second electrical connect structure and the insulation layer, causing reaction of the metal cations to substantially convert the metal cations into electrically neutral materials; and removing the reacted metal cations from the insulation layer.

公开(公告)号：US09698081B2

公开(公告)日：2017-07-04

申请号：US15264245

申请日：2016-09-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Wen-Ching Tsai

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L21/311 ,  H01L23/31 ,  H01L21/56 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/481 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/48 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02122 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/24146 ,  H01L2224/80001 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00014

Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.

公开(公告)号：US20170148713A1

公开(公告)日：2017-05-25

申请号：US15369443

申请日：2016-12-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Atsuko IIDA ,  Tadahiro Sasaki ,  Nobuto Managaki ,  Yutaka Onozuka ,  Hiroshi Yamada

IPC: H01L23/498 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L23/04 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/60 ,  H01L23/66 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0657 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/24195 ,  H01L2224/82106 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2924/15788 ,  H01L2924/19105 ,  H01P1/20 ,  H01P1/2005 ,  H01P1/202 ,  H01P5/028 ,  H05K1/117 ,  H05K3/403 ,  H05K2201/0919 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/0231 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079

Abstract: A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.