公开(公告)号：US20120228766A1

公开(公告)日：2012-09-13

申请号：US13476899

申请日：2012-05-21

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L23/48

CPC classification number: H01L24/14 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.

Abstract translation: 半导体器件具有具有管芯凸块焊盘的半导体管芯和具有集成凸块焊盘的迹线的衬底。 在芯片凸块焊盘或集成凸块焊盘之间间隙地形成焊接掩模贴片。 焊接掩模贴片包含不可润湿的材料。 导电凸块材料沉积在集成的凸块焊盘或模具凸块焊盘上。 半导体管芯安装在衬底上，使得导电凸块材料设置在管芯凸块焊盘和集成的凸块焊盘之间。 凸块材料在集成的凸块焊盘周围没有焊接掩模的情况下回流以形成半导体管芯和衬底之间的互连。 焊接掩模贴片将导电凸块材料限制在回流焊中芯片凸块焊盘或集成凸块焊盘的占位面积内。 互连可以具有不可熔的基底和易熔盖。

公开(公告)号：US20120211882A9

公开(公告)日：2012-08-23

申请号：US12963919

申请日：2010-12-09

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L21/76885 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/10145 ,  H01L2224/10175 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/81097 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81208 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate.

Abstract translation: 半导体器件具有具有多个具有互连部位的多个导体迹线的多个管芯凸块焊盘和衬底的半导体管芯。 在芯片凸块焊盘或互连部位之间间隙地形成焊接掩模贴片。 导电凸块材料沉积在互连部位或模具凸块上。 将半导体管芯安装到衬底上，使得导电凸块材料设置在管芯凸块焊盘和互连部位之间。 导电凸块材料在管芯凸块焊盘或互连部位周围没有焊接掩模回流，以在半导体管芯和衬底之间形成互连结构。 焊接掩模贴片将导电凸块材料限制在管芯凸块焊盘或互连部位内。 互连结构可以包括可熔部分和不可熔部分。 密封剂沉积在半导体管芯和衬底之间。

公开(公告)号：US08215969B2

公开(公告)日：2012-07-10

申请号：US12144658

申请日：2008-06-24

Applicant: Sheng-Shu Yang ,  Shyh-Ming Chang

Inventor： Sheng-Shu Yang ,  Shyh-Ming Chang

IPC: H01R4/58

CPC classification number: H05K3/4007 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05567 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13008 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13078 ,  H01L2224/1319 ,  H01L2224/13562 ,  H01L2224/13563 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/1401 ,  H01L2224/1411 ,  H01L2224/1415 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/9211 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01033 ,  H01L2924/15788 ,  H01R12/714 ,  H05K3/325 ,  H05K3/368 ,  H05K2201/0367 ,  H05K2201/09909 ,  Y10S439/931 ,  Y10T29/49155 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A contact structure disposed on a substrate is provided. The contact structure includes a pad, a polymer bump and a conductive layer. The pad is on the substrate. The polymer bump having a curve surface and a steep surface connecting with the curve surface is disposed on the substrate. The polymer bump is covered by the conductive layer and the conductive layer is electrically connected with the pad.

Abstract translation: 设置在基板上的接触结构。 接触结构包括垫，聚合物凸块和导电层。 衬垫在衬底上。 具有弯曲表面和与曲面连接的陡峭表面的聚合物凸块设置在基板上。 聚合物凸块被导电层覆盖，并且导电层与焊盘电连接。

公开(公告)号：US20120160543A1

公开(公告)日：2012-06-28

申请号：US13332925

申请日：2011-12-21

Applicant: Masaya NAKANISHI ,  Yasuhito TANABE ,  Hidemitsu WATANABE

Inventor： Masaya NAKANISHI ,  Yasuhito TANABE ,  Hidemitsu WATANABE

IPC: H05K1/02

CPC classification number: H05K3/0064 ,  H05K3/28 ,  H05K2201/09063 ,  H05K2201/09909 ,  H05K2201/09936

Abstract: A circuit board to be attached to a support such as a case body is provided. The circuit board has formed therein a mounting hole which is so designed as to permit a thermally deformable stud to protrude through the mounting hole and also to be thermoplastically staked to mount the board to the support. A layer is printed on the board by means of silk screen printing at a distance from the mounting hole. In a case where a moisture-proof and insulating material is applied over a surface of the board, the printed layer servers to block a flow of the moisture-proof and insulating material into the mounting hole. This avoids a reduction in strength of fastening the board to the support. The printed layer may also be used in visually inspecting a failure in thermoplastic staking to mount the board to the support.

Abstract translation: 提供要附接到诸如壳体的支撑件的电路板。 电路板上形成有安装孔，该安装孔被设计成允许可热变形的螺柱突出穿过安装孔，并且还被热塑性地固定以将板安装到支撑件上。 通过与安装孔距离一段距离的丝网印刷，印刷在印版上的层。 在将防潮绝缘材料施加在板的表面上的情况下，印刷层服务器阻止防潮绝缘材料流入安装孔。 这避免了将板紧固到支撑件上的强度的降低。 印刷层也可用于目视检查热塑性塑料的破坏以将板安装到支撑体上。

公开(公告)号：US20120106110A1

公开(公告)日：2012-05-03

申请号：US13306347

申请日：2011-11-29

Applicant: Shinji MORIYAMA ,  Tomio YAMADA

Inventor： Shinji MORIYAMA ,  Tomio YAMADA

IPC: H05K7/02

CPC classification number: H01L23/13 ,  H01L23/10 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H03G3/3042 ,  H05K1/0263 ,  H05K1/141 ,  H05K1/183 ,  H05K3/3405 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/10371 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include ones which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

公开(公告)号：US20120106032A1

公开(公告)日：2012-05-03

申请号：US13345227

申请日：2012-01-06

Applicant: John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Anthony P. Chacko ,  Gregory J. Dunn

Inventor： John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Anthony P. Chacko ,  Gregory J. Dunn

IPC: H01G9/025 ,  H01G9/04 ,  H01G9/15 ,  H01G7/00

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G9/042 ,  H01G9/045 ,  H01G9/15 ,  H05K3/429 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09909 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/435

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract translation: 一种用于形成具有电容的叠层的方法和由此形成的层压体。 该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。 在电介质上形成导电层。 处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。 在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。

公开(公告)号：US08134082B2

公开(公告)日：2012-03-13

申请号：US12377134

申请日：2008-05-28

Applicant: Tadashi Nakamura ,  Fumio Echigo ,  Takayuki Kita ,  Kota Fukasawa ,  Shogo Hirai

Inventor： Tadashi Nakamura ,  Fumio Echigo ,  Takayuki Kita ,  Kota Fukasawa ,  Shogo Hirai

IPC: H05K3/02 ,  H05K3/10 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K3/4697 ,  H05K1/183 ,  H05K1/189 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4691 ,  H05K3/4694 ,  H05K2201/09145 ,  H05K2201/09845 ,  H05K2201/09909 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/2018 ,  H05K2203/061 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A solid printed circuit board is manufactured by bonding upper and lower printed circuit boards having different shapes and provided with wirings formed on surfaces thereof. A bonding layer is made of insulating material containing thermosetting resin and inorganic filler dispersed therein, and has a via-conductor made of conductive paste filling a through-hole perforated in a predetermined position of the bonding layer. This circuit board provides a packaging configuration achieving small size and thickness and three-dimensional mounting suitable for semiconductors of high performance and multiple-pin structure.

Abstract translation: 通过粘接具有不同形状的上下印刷电路板并且在其表面上形成布线来制造实心印刷电路板。 接合层由含有分散在其中的热固性树脂和无机填料的绝缘材料制成，并且具有填充在接合层的预定位置穿孔的通孔的由导电膏制成的通孔导体。 该电路板提供了实现小尺寸和厚度的三维安装，适用于高性能和多引脚结构半导体的封装结构。

公开(公告)号：US08124881B2

公开(公告)日：2012-02-28

申请号：US12394889

申请日：2009-02-27

Applicant: Noriyuki Shirasawa

Inventor： Noriyuki Shirasawa

IPC: H05K1/16 ,  H05K7/00 ,  H01L23/48

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/13 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H05K3/3452 ,  H05K2201/09063 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49121 ,  Y10T29/49126 ,  H01L2924/00

Abstract: A printed board comprising a packaging surface on which an electronic component is packaged, an adhesion prohibited portion which is provided at a region of the printed board different from a region where the electronic component is provided, and to which adhesion of the adhesive material is prohibited, and a blocking step portion which is formed at a region between the region where the electronic component is provided and the region where the adhesion prohibited portion is provided, which blocks any adhesive material which has spilled out from between the bottom surface of the electronic component and the packaging surface from reaching the adhesion prohibited portion.

Abstract translation: 一种印刷电路板，包括封装有电子部件的封装表面，设置在与设置有电子部件的区域不同的印刷电路板的区域的粘合禁止部分，并且粘合剂材料的粘合被禁止 以及阻挡台阶部，其形成在设置有电子部件的区域与设置有防粘连部的区域之间的区域，该阻挡台阶部阻挡从电子部件的底面之间溅出的任何粘接材料 并且包装表面到达不粘附部分。

公开(公告)号：US08084852B2

公开(公告)日：2011-12-27

申请号：US13020767

申请日：2011-02-03

Applicant: Shinji Moriyama ,  Tomio Yamada

Inventor： Shinji Moriyama ,  Tomio Yamada

IPC: H01L23/52 ,  H01L23/04 ,  H01L23/053 ,  H01L23/12 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/13 ,  H01L23/10 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H03G3/3042 ,  H05K1/0263 ,  H05K1/141 ,  H05K1/183 ,  H05K3/3405 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/10371 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

公开(公告)号：US08078284B2

公开(公告)日：2011-12-13

申请号：US11523965

申请日：2006-09-19

Applicant: Robert J. Greenberg ,  Matthew J. McMahon ,  James Singleton Little ,  Kelly H. McClure ,  Brian V. Mech ,  Neil Hamilton Talbot ,  Jordan M. Neysmith

Inventor： Robert J. Greenberg ,  Matthew J. McMahon ,  James Singleton Little ,  Kelly H. McClure ,  Brian V. Mech ,  Neil Hamilton Talbot ,  Jordan M. Neysmith

IPC: A61N1/00

CPC classification number: A61N1/36046 ,  A61N1/0543 ,  A61N1/37223 ,  H05K1/028 ,  H05K1/0281 ,  H05K1/118 ,  H05K3/0014 ,  H05K3/28 ,  H05K2201/0133 ,  H05K2201/09018 ,  H05K2201/09145 ,  H05K2201/09909 ,  H05K2201/2009 ,  H05K2203/1105 ,  H05K2203/1476 ,  H05K2203/302 ,  Y10T29/49158

Abstract: Polymer materials are useful as electrode array bodies for neural stimulation. They are particularly useful for retinal stimulation to create artificial vision, cochlear stimulation to create artificial hearing, and cortical stimulation, and many related purposes. The pressure applied against the retina, or other neural tissue, by an electrode array is critical. Too little pressure causes increased electrical resistance, along with electric field dispersion. Too much pressure may block blood flow. Common flexible circuit fabrication techniques generally require that a flexible circuit electrode array be made flat. Since neural tissue is almost never flat, a flat array will necessarily apply uneven pressure. Further, the edges of a flexible circuit polymer array may be sharp and cut the delicate neural tissue. By applying the right amount of heat to a completed array, a curve can be induced. With a thermoplastic polymer it may be further advantageous to repeatedly heat the flexible circuit in multiple molds, each with a decreasing radius. Further, it is advantageous to add material along the edges. It is further advantageous to provide a fold or twist in the flexible circuit array. Additional material may be added inside and outside the fold to promote a good seal with tissue.

Abstract translation: 聚合物材料可用作神经刺激的电极阵列体。 它们特别有用于视网膜刺激以产生人造视觉，耳蜗刺激以产生人造听觉和皮质刺激以及许多相关目的。 通过电极阵列对视网膜或其他神经组织施加的压力是至关重要的。 太小的压力会导致电阻增加以及电场分散。 太大的压力可能会阻止血液流动。 通常的柔性电路制造技术通常需要使柔性电路电极阵列平坦。 由于神经组织几乎从不平坦，平面阵列必然会施加不均匀的压力。 此外，柔性电路聚合物阵列的边缘可以是尖锐的并切割精细的神经组织。 通过将适量的热应用于完整的阵列，可以引起曲线。 对于热塑性聚合物，可以进一步有利的是在多个模具中反复加热柔性电路，每个模具具有减小的半径。 此外，沿着边缘添加材料是有利的。 在柔性电路阵列中提供折叠或扭曲是更有利的。 可以在折叠内部和外部添加附加材料以促进与组织的良好密封。