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    TRANSISTORS WITH METAL GATE AND METHODS FOR FORMING THE SAME
    9.
    发明申请
    TRANSISTORS WITH METAL GATE AND METHODS FOR FORMING THE SAME 有权
    具有金属栅的晶体管及其形成方法

    公开(公告)号：US20100155849A1

    公开(公告)日：2010-06-24

    申请号：US12343307

    申请日：2008-12-23

    Applicant: Chung-Shi LIU ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

    Inventor： Chung-Shi LIU ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

    IPC: H01L27/092 ,  H01L21/28

    CPC classification number: H01L29/517 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513

    Abstract: A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MCxOy) containing layer is formed over the at least one first gate dielectric layer, wherein the transition-metal (M) has an atomic percentage of about 40 at. % or more. A first gate is formed over the first transition-metal oxycarbide containing layer. At least one first doped region is formed within the substrate and adjacent to a sidewall of the first gate.

    Abstract translation: 半导体器件包括在衬底上的至少一个第一栅极电介质层。 在所述至少一个第一栅极介电层上形成含有第一过渡金属碳氧化物（MCxOy）的层，其中所述过渡金属（M）的原子百分比为约40原子。 ％ 或者更多。 在第一过渡金属含碳氧化物层上形成第一栅极。 至少一个第一掺杂区域形成在衬底内并且邻近第一栅极的侧壁。

    ADVANCED METAL GATE METHOD AND DEVICE
    10.
    发明申请
    ADVANCED METAL GATE METHOD AND DEVICE 有权
    高级金属门的方法和装置

    公开(公告)号：US20100084718A1

    公开(公告)日：2010-04-08

    申请号：US12354558

    申请日：2009-01-15

    Applicant: Chung-Shi LIU ,  Hsiang-Yi WANG ,  Cheng-Tung LIN ,  Chen-Hua YU

    Inventor： Chung-Shi LIU ,  Hsiang-Yi WANG ,  Cheng-Tung LIN ,  Chen-Hua YU

    IPC: H01L29/78 ,  H01L21/283 ,  H01L21/336

    CPC classification number: H01L21/28088 ,  H01L21/265 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/78

    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.

    Abstract translation: 本公开提供一种制造半导体器件的方法，其包括在衬底上形成高k电介质，在高k电介质上形成第一金属层，在第一金属层上形成第二金属层，形成第一硅 在所述第二金属层上方，将多个离子注入到所述第一硅层中，并且所述第二金属层覆盖在所述基板的第一区域上，在所述第一硅层上形成第二硅层，在所述第一区上形成第一栅极结构 以及在第二区域上的第二栅极结构，执行使所述第二金属层与所述第一硅层反应以在所述第一和第二栅极结构中分别形成硅化物层的退火处理，并将所述离子驱动到 第一栅极结构中的第一金属层和高k电介质。

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