专利检索 ap:("Yi-Yang LEI" OR "Hung-Jui KUO" OR "Chung-Shi LIU" OR "Mirng-Ji LII" OR "Chen-Hua YU") AND inv:"Chung-Shi LIU" 第 1 页

1.

发明申请
CLEANING RESIDUAL MOLDING COMPOUND ON SOLDER BUMPS 有权
标题翻译：焊剂上清洁残留模塑料

公开(公告)号：US20130034956A1

公开(公告)日：2013-02-07

申请号：US13198767

申请日：2011-08-05

申请人： Yi-Yang LEI , Hung-Jui KUO , Chung-Shi LIU , Mirng-Ji LII , Chen-Hua YU

发明人： Yi-Yang LEI , Hung-Jui KUO , Chung-Shi LIU , Mirng-Ji LII , Chen-Hua YU

IPC分类号： H01L21/28

CPC分类号： H01L24/11 , H01L23/3171 , H01L23/3192 , H01L24/02 , H01L24/05 , H01L24/13 , H01L2224/0239 , H01L2224/0401 , H01L2224/05024 , H01L2224/05569 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05687 , H01L2224/11334 , H01L2224/11849 , H01L2224/119 , H01L2224/1191 , H01L2224/131 , H01L2224/13111 , H01L2924/00014 , H01L2924/10253 , H01L2924/12042 , H01L2924/181 , H01L2924/01029 , H01L2924/01013 , H01L2924/01028 , H01L2924/014 , H01L2924/01047 , H01L2224/1181 , H01L2924/04953 , H01L2924/04941 , H01L2924/00 , H01L2224/05552

摘要： A method of forming wafer-level chip scale packaging solder bumps on a wafer substrate involves cleaning the surface of the solder bumps using a laser to remove any residual molding compound from the surface of the solder bumps after the solder bumps are reflowed and a liquid molding compound is applied and cured.

摘要翻译： 在晶片衬底上形成晶片级芯片级封装焊料凸块的方法包括使用激光清洗焊料凸块的表面，以在焊料凸点回流之后从焊料凸块的表面去除残留的模塑料，并且液态模塑化合物被施用和固化。

2.

发明申请
METHOD OF FORMING ELECTRICAL CONNECTIONS 有权
标题翻译：形成电气连接的方法

公开(公告)号：US20110027944A1

公开(公告)日：2011-02-03

申请号：US12768025

申请日：2010-04-27

申请人： Chung-Shi LIU , Shin-Puu JENG , Mirng-Ji LII , Chen-Hua YU

发明人： Chung-Shi LIU , Shin-Puu JENG , Mirng-Ji LII , Chen-Hua YU

IPC分类号： H01L21/768 , H01L21/56

CPC分类号： H01L23/3171 , H01L21/563 , H01L23/525 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/10126 , H01L2224/1147 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/73203 , H01L2924/00013 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2224/13099

摘要： A method of forming electrical connections to a semiconductor wafer. A semiconductor wafer comprising an insulation layer is provided. The insulation layer has a surface. A patterned mask layer is formed over the surface of the insulation layer. The patterned mask layer exposes portions of the surface of the insulation layer through a plurality of holes. The portions of the plurality of holes are filled with a metal material comprising copper to form elongated columns of the metal material. The elongated columns of the metal material have a sidewall surface. The patterned mask layer is removed to expose the sidewall surface of the elongated columns of the metal material. A protection layer is formed on the exposed sidewall surface of the elongated columns of the metal material.

摘要翻译： 形成与半导体晶片的电连接的方法。提供了包括绝缘层的半导体晶片。绝缘层具有表面。在绝缘层的表面上形成图案化掩模层。图案化掩模层通过多个孔暴露绝缘层的表面的部分。多个孔的部分填充有包含铜的金属材料以形成细长的金属材料柱。金属材料的细长柱具有侧壁表面。去除图案化的掩模层以暴露金属材料的细长柱的侧壁表面。保护层形成在金属材料的细长柱的暴露的侧壁表面上。

3.

发明申请
PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME 有权
标题翻译：包装结构及其形成方法

公开(公告)号：US20130270700A1

公开(公告)日：2013-10-17

申请号：US13526073

申请日：2012-06-18

申请人： Chen-Hua YU , Mirng-Ji LII , Chung-Shi LIU , Meng-Tse CHEN , Wei-Hung LIN , Ming-Da CHENG

发明人： Chen-Hua YU , Mirng-Ji LII , Chung-Shi LIU , Meng-Tse CHEN , Wei-Hung LIN , Ming-Da CHENG

IPC分类号： H01L23/498 , H01L21/78

CPC分类号： H01L24/05 , B23K35/001 , B23K35/0222 , B23K35/22 , B23K35/262 , B23K35/3613 , H01L21/561 , H01L23/3135 , H01L23/3178 , H01L23/498 , H01L23/49816 , H01L24/08 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/03 , H01L25/0652 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05572 , H01L2224/05611 , H01L2224/06181 , H01L2224/08113 , H01L2224/1184 , H01L2224/13005 , H01L2224/13014 , H01L2224/13022 , H01L2224/13023 , H01L2224/13026 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/1355 , H01L2224/13561 , H01L2224/1357 , H01L2224/13582 , H01L2224/136 , H01L2224/13666 , H01L2224/1412 , H01L2224/14181 , H01L2224/16104 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17051 , H01L2224/48091 , H01L2224/48227 , H01L2224/81815 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/381 , H01L2924/3841 , H01L2924/00 , H01L2224/81 , H01L2924/01047 , H01L2924/01029 , H01L2924/01083 , H01L2924/013 , H01L2924/206 , H01L2224/05552 , H01L2924/00012

摘要： The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small.

摘要翻译： 形成封装封装（PoP）结构的机构的所述实施例包括将具有非焊料金属球的连接器与包装衬底结合。非焊接金属球可以包括焊料涂层。具有非焊接金属球的连接器可以基本保持连接器的形状并控制上部和下部封装之间的结合结构的高度。具有非焊接金属球的连接器也不太可能导致连接器之间的桥接或接合连接器的断开（或冷接头）。结果，可以将具有非焊接金属球的连接器的间距保持较小。

4.

发明申请
BUMP STRUCTURE WITH BARRIER LAYER ON POST-PASSIVATION INTERCONNECT 有权
标题翻译：在盲法互连后的障碍层的BUMP结构

公开(公告)号：US20120326298A1

公开(公告)日：2012-12-27

申请号：US13167946

申请日：2011-06-24

申请人： Chen-Fa LU , Chung-Shi LIU , Mirng-Ji LII , Chen-Hua YU

发明人： Chen-Fa LU , Chung-Shi LIU , Mirng-Ji LII , Chen-Hua YU

IPC分类号： H01L23/485 , H01L21/283

CPC分类号： H01L24/03 , H01L23/3114 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0346 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05571 , H01L2224/05583 , H01L2224/05609 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/11334 , H01L2224/11849 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16147 , H01L2224/16237 , H01L2224/81191 , H01L2224/81411 , H01L2224/81413 , H01L2224/81416 , H01L2224/81439 , H01L2224/81447 , H01L2224/81455 , H01L2224/81815 , H01L2224/8191 , H01L2924/00014 , H01L2924/01327 , H01L2924/12041 , H01L2924/12042 , H01L2924/15788 , H01L2924/01029 , H01L2924/00012 , H01L2924/01082 , H01L2924/01046 , H01L2924/01079 , H01L2924/01047 , H01L2924/014 , H01L2924/00 , H01L2224/05552

摘要： A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer.

摘要翻译： 半导体器件包括在焊料凸块和钝化后互连（PPI）层之间的阻挡层。阻挡层由无电镀镍（Ni）层，无电解钯（Pd）层或浸金（Au）层中的至少一种形成。

5.

发明申请
SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体封装及其形成方法

公开(公告)号：US20130093076A1

公开(公告)日：2013-04-18

申请号：US13272434

申请日：2011-10-13

申请人： Wei-Hung LIN , Ming-Da CHENG , Chung-Shi LIU , Mirng-Ji LII , Chen-Hua YU

发明人： Wei-Hung LIN , Ming-Da CHENG , Chung-Shi LIU , Mirng-Ji LII , Chen-Hua YU

IPC分类号： H01L23/498 , B23K1/20

CPC分类号： H01L23/49894 , H01L21/4864 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05647 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/16238 , H01L2224/73204 , H01L2224/81022 , H01L2224/81191 , H01L2224/81815 , H01L2924/1305 , H01L2924/13091 , H01L2924/00014 , H01L2924/01073 , H01L2924/01049 , H01L2924/0105 , H01L2924/0103 , H01L2924/01025 , H01L2924/01024 , H01L2924/01022 , H01L2924/01032 , H01L2924/01038 , H01L2924/01078 , H01L2924/01012 , H01L2924/01013 , H01L2924/0104 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2924/01082 , H01L2924/01083 , H01L2924/01079 , H01L2924/01051 , H01L2924/04941 , H01L2924/04953 , H01L2924/00

摘要： A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package.

摘要翻译： 半导体封装的方法包括提供具有涂覆有有机可焊性防腐剂（OSP）层的导电迹线的衬底，从导电迹线去除OSP层，然后将芯片耦合到衬底以形成半导体封装。

6.

发明申请
SEMICONDUCTOR DEVICE HAVING UNDER-BUMP METALLIZATION (UBM) STRUCTURE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：具有底层金属化（UBM）结构的半导体器件及其形成方法

公开(公告)号：US20120098124A1

公开(公告)日：2012-04-26

申请号：US13033780

申请日：2011-02-24

申请人： Yi-Wen WU , Hung-Jui KUO , Chien Ling HWANG , Chung-Shi LIU

发明人： Yi-Wen WU , Hung-Jui KUO , Chien Ling HWANG , Chung-Shi LIU

IPC分类号： H01L23/498 , H01L21/28

CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03424 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/0361 , H01L2224/03901 , H01L2224/03912 , H01L2224/0401 , H01L2224/05018 , H01L2224/05027 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05559 , H01L2224/05564 , H01L2224/05572 , H01L2224/05655 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13006 , H01L2224/13111 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/01046 , H01L2924/01028 , H01L2924/0105 , H01L2924/0103 , H01L2924/01083 , H01L2924/01049 , H01L2924/01051 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552

摘要： A semiconductor device has a UBM (under-bump metallization) structure underlying and electrically connected to a solder bump. The UBM structure has a first metallization layer with a first cross-sectional dimension d1, a second metallization layer with a second cross-sectional dimension d2 formed on the first metallization layer, and a third metallization layer with a third cross-sectional dimension d3 formed on the second metallization layer, in which d1 is greater than d3, and d3 is greater than d2.

摘要翻译： 半导体器件具有下面的并且与焊料凸块电连接的UBM（凸点下金属化）结构。 UBM结构具有第一横截面尺寸d1的第一金属化层，形成在第一金属化层上的第二横截面尺寸d2的第二金属化层，以及形成第三横截面尺寸d3的第三金属化层在第二金属化层上，其中d1大于d3，d3大于d2。

7.

发明申请
CONDUCTIVE PILLAR STRUCTURE 审中-公开
标题翻译：导电支柱结构

公开(公告)号：US20120091574A1

公开(公告)日：2012-04-19

申请号：US12904506

申请日：2010-10-14

申请人： Chih-Wei LIN , Ming-Da CHENG , Wen-Hsiung LU , Meng-Wei CHOU , Hung-Jui KUO , Chung-Shi LIU

发明人： Chih-Wei LIN , Ming-Da CHENG , Wen-Hsiung LU , Meng-Wei CHOU , Hung-Jui KUO , Chung-Shi LIU

IPC分类号： H01L23/48 , H01L21/768

CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0341 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05559 , H01L2224/05564 , H01L2224/05647 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11472 , H01L2224/13006 , H01L2224/13007 , H01L2224/13017 , H01L2224/13023 , H01L2224/13147 , H01L2224/16 , H01L2224/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/04941 , H01L2924/04953 , H01L2924/01028 , H01L2924/01044 , H01L2924/01025 , H01L2924/01022 , H01L2924/01032 , H01L2924/00 , H01L2224/05552

摘要： The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate having an opening over the contact pad; and a conductive pillar over the opening of the passivation layer, wherein the conductive pillar comprises an upper portion substantially perpendicular to a surface of the substrate and a lower portion having tapered sidewalls.

摘要翻译： 本发明涉及半导体器件的凸块结构。半导体器件的示例性结构包括衬底; 衬底上的接触垫; 钝化层，其在所述衬底上延伸，在所述接触焊盘上具有开口; 以及在所述钝化层的开口上的导电柱，其中所述导电柱包括基本上垂直于所述衬底的表面的上部和具有锥形侧壁的下部。

8.

发明申请
INTEGRATED CIRCUITS INCLUDING METAL GATES AND FABRICATION METHODS THEREOF 有权
标题翻译：集成电路，包括金属门和其制造方法

公开(公告)号：US20110108922A1

公开(公告)日：2011-05-12

申请号：US12846474

申请日：2010-07-29

申请人： Chung-Shi LIU , Chen-Hua YU

发明人： Chung-Shi LIU , Chen-Hua YU

IPC分类号： H01L27/092 , H01L21/8238

CPC分类号： H01L27/092 , H01L21/265 , H01L21/28088 , H01L21/8238 , H01L21/823835 , H01L21/823842 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/66575

摘要： A method of forming an integrated circuit is provided. The method includes forming a gate electrode of an NMOS transistor over a substrate by a gate-first process. A gate electrode of a PMOS transistor is formed over the substrate by a gate-last process.

摘要翻译： 提供一种形成集成电路的方法。该方法包括通过栅极首先工艺在衬底上形成NMOS晶体管的栅电极。 PMOS晶体管的栅极通过栅极最后工艺形成在衬底的上方。