公开(公告)号：US20110027944A1

公开(公告)日：2011-02-03

申请号：US12768025

申请日：2010-04-27

Applicant: Chung-Shi LIU ,  Shin-Puu JENG ,  Mirng-Ji LII ,  Chen-Hua YU

Inventor： Chung-Shi LIU ,  Shin-Puu JENG ,  Mirng-Ji LII ,  Chen-Hua YU

IPC: H01L21/768 ,  H01L21/56

CPC classification number: H01L23/3171 ,  H01L21/563 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/73203 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A method of forming electrical connections to a semiconductor wafer. A semiconductor wafer comprising an insulation layer is provided. The insulation layer has a surface. A patterned mask layer is formed over the surface of the insulation layer. The patterned mask layer exposes portions of the surface of the insulation layer through a plurality of holes. The portions of the plurality of holes are filled with a metal material comprising copper to form elongated columns of the metal material. The elongated columns of the metal material have a sidewall surface. The patterned mask layer is removed to expose the sidewall surface of the elongated columns of the metal material. A protection layer is formed on the exposed sidewall surface of the elongated columns of the metal material.

Abstract translation: 形成与半导体晶片的电连接的方法。 提供了包括绝缘层的半导体晶片。 绝缘层具有表面。 在绝缘层的表面上形成图案化掩模层。 图案化掩模层通过多个孔暴露绝缘层的表面的部分。 多个孔的部分填充有包含铜的金属材料以形成细长的金属材料柱。 金属材料的细长柱具有侧壁表面。 去除图案化的掩模层以暴露金属材料的细长柱的侧壁表面。 保护层形成在金属材料的细长柱的暴露的侧壁表面上。

公开(公告)号：US20100084718A1

公开(公告)日：2010-04-08

申请号：US12354558

申请日：2009-01-15

Applicant: Chung-Shi LIU ,  Hsiang-Yi WANG ,  Cheng-Tung LIN ,  Chen-Hua YU

Inventor： Chung-Shi LIU ,  Hsiang-Yi WANG ,  Cheng-Tung LIN ,  Chen-Hua YU

IPC: H01L29/78 ,  H01L21/283 ,  H01L21/336

CPC classification number: H01L21/28088 ,  H01L21/265 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/78

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.

Abstract translation: 本公开提供一种制造半导体器件的方法，其包括在衬底上形成高k电介质，在高k电介质上形成第一金属层，在第一金属层上形成第二金属层，形成第一硅 在所述第二金属层上方，将多个离子注入到所述第一硅层中，并且所述第二金属层覆盖在所述基板的第一区域上，在所述第一硅层上形成第二硅层，在所述第一区上形成第一栅极结构 以及在第二区域上的第二栅极结构，执行使所述第二金属层与所述第一硅层反应以在所述第一和第二栅极结构中分别形成硅化物层的退火处理，并将所述离子驱动到 第一栅极结构中的第一金属层和高k电介质。

公开(公告)号：US20130093076A1

公开(公告)日：2013-04-18

申请号：US13272434

申请日：2011-10-13

Applicant: Wei-Hung LIN ,  Ming-Da CHENG ,  Chung-Shi LIU ,  Mirng-Ji LII ,  Chen-Hua YU

Inventor： Wei-Hung LIN ,  Ming-Da CHENG ,  Chung-Shi LIU ,  Mirng-Ji LII ,  Chen-Hua YU

IPC: H01L23/498 ,  B23K1/20

CPC classification number: H01L23/49894 ,  H01L21/4864 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05647 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81022 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01024 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01079 ,  H01L2924/01051 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00

Abstract: A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package.

Abstract translation: 半导体封装的方法包括提供具有涂覆有有机可焊性防腐剂（OSP）层的导电迹线的衬底，从导电迹线去除OSP层，然后将芯片耦合到衬底以形成半导体封装。

公开(公告)号：US20110049705A1

公开(公告)日：2011-03-03

申请号：US12786698

申请日：2010-05-25

Applicant: Chung-Shi LIU ,  Chen-Hua YU

Inventor： Chung-Shi LIU ,  Chen-Hua YU

IPC: H01L23/498

CPC classification number: H01L23/53228 ,  H01L23/53238 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01028 ,  H01L2924/0105

Abstract: A copper post is formed in a passivation layer to electrically connect an underlying bond pad region, and extends to protrude from the passivation layer. A protection layer is formed on a sidewall surface or a top surface of the copper post in a self-aligned manner. The protection layer is a manganese-containing oxide layer, a manganese-containing nitride layer or a manganese-containing oxynitride layer.

Abstract translation: 铜柱形成在钝化层中以电连接下面的焊盘区域，并且延伸到从钝化层突出。 保护层以自对准方式形成在铜柱的侧壁表面或顶表面上。 保护层是含锰氧化物层，含锰氮化物层或含锰氮氧化物层。

公开(公告)号：US20130270700A1

公开(公告)日：2013-10-17

申请号：US13526073

申请日：2012-06-18

Applicant: Chen-Hua YU ,  Mirng-Ji LII ,  Chung-Shi LIU ,  Meng-Tse CHEN ,  Wei-Hung LIN ,  Ming-Da CHENG

Inventor： Chen-Hua YU ,  Mirng-Ji LII ,  Chung-Shi LIU ,  Meng-Tse CHEN ,  Wei-Hung LIN ,  Ming-Da CHENG

IPC: H01L23/498 ,  H01L21/78

CPC classification number: H01L24/05 ,  B23K35/001 ,  B23K35/0222 ,  B23K35/22 ,  B23K35/262 ,  B23K35/3613 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/498 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/06181 ,  H01L2224/08113 ,  H01L2224/1184 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1355 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13666 ,  H01L2224/1412 ,  H01L2224/14181 ,  H01L2224/16104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/013 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small.

Abstract translation: 形成封装封装（PoP）结构的机构的所述实施例包括将具有非焊料金属球的连接器与包装衬底结合。 非焊接金属球可以包括焊料涂层。 具有非焊接金属球的连接器可以基本保持连接器的形状并控制上部和下部封装之间的结合结构的高度。 具有非焊接金属球的连接器也不太可能导致连接器之间的桥接或接合连接器的断开（或冷接头）。 结果，可以将具有非焊接金属球的连接器的间距保持较小。

公开(公告)号：US20130034956A1

公开(公告)日：2013-02-07

申请号：US13198767

申请日：2011-08-05

Applicant: Yi-Yang LEI ,  Hung-Jui KUO ,  Chung-Shi LIU ,  Mirng-Ji LII ,  Chen-Hua YU

Inventor： Yi-Yang LEI ,  Hung-Jui KUO ,  Chung-Shi LIU ,  Mirng-Ji LII ,  Chen-Hua YU

IPC: H01L21/28

CPC classification number: H01L24/11 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/1191 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/1181 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of forming wafer-level chip scale packaging solder bumps on a wafer substrate involves cleaning the surface of the solder bumps using a laser to remove any residual molding compound from the surface of the solder bumps after the solder bumps are reflowed and a liquid molding compound is applied and cured.

Abstract translation: 在晶片衬底上形成晶片级芯片级封装焊料凸块的方法包括使用激光清洗焊料凸块的表面，以在焊料凸点回流之后从焊料凸块的表面去除残留的模塑料，并且液态模塑 化合物被施用和固化。

公开(公告)号：US20120326298A1

公开(公告)日：2012-12-27

申请号：US13167946

申请日：2011-06-24

Applicant: Chen-Fa LU ,  Chung-Shi LIU ,  Mirng-Ji LII ,  Chen-Hua YU

Inventor： Chen-Fa LU ,  Chung-Shi LIU ,  Mirng-Ji LII ,  Chen-Hua YU

IPC: H01L23/485 ,  H01L21/283

CPC classification number: H01L24/03 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05583 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer.

Abstract translation: 半导体器件包括在焊料凸块和钝化后互连（PPI）层之间的阻挡层。 阻挡层由无电镀镍（Ni）层，无电解钯（Pd）层或浸金（Au）层中的至少一种形成。

公开(公告)号：US20110108922A1

公开(公告)日：2011-05-12

申请号：US12846474

申请日：2010-07-29

Applicant: Chung-Shi LIU ,  Chen-Hua YU

Inventor： Chung-Shi LIU ,  Chen-Hua YU

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/265 ,  H01L21/28088 ,  H01L21/8238 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575

Abstract: A method of forming an integrated circuit is provided. The method includes forming a gate electrode of an NMOS transistor over a substrate by a gate-first process. A gate electrode of a PMOS transistor is formed over the substrate by a gate-last process.

Abstract translation: 提供一种形成集成电路的方法。 该方法包括通过栅极首先工艺在衬底上形成NMOS晶体管的栅电极。 PMOS晶体管的栅极通过栅极最后工艺形成在衬底的上方。

公开(公告)号：US20110260317A1

公开(公告)日：2011-10-27

申请号：US12765250

申请日：2010-04-22

Applicant: Wen-Hsiung LU ,  Ming-Da CHENG ,  Chih-Wei LIN ,  Jacky CHANG ,  Chung-Shi LIU ,  Chen-Hua YU

Inventor： Wen-Hsiung LU ,  Ming-Da CHENG ,  Chih-Wei LIN ,  Jacky CHANG ,  Chung-Shi LIU ,  Chen-Hua YU

IPC: H01L23/50 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11906 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13455 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A copper pillar bump has a sidewall protection layer formed of an electrolytic metal layer. The electrolytic metal layer is an electrolytic nickel layer, an electrolytic gold layer, and electrolytic copper layer, or an electrolytic silver layer.

Abstract translation: 铜柱凸起具有由电解金属层形成的侧壁保护层。 电解金属层是电解镍层，电解金层，电解铜层或电解银层。

公开(公告)号：US20130147032A1

公开(公告)日：2013-06-13

申请号：US13313747

申请日：2011-12-07

Applicant: Shin-Puu JENG ,  Wei-Cheng WU ,  Shang-Yun HOU ,  Chen-Hua YU ,  Tzuan-Horng LIU ,  Tzu-Wei CHIU ,  Kuo-Ching HSU

Inventor： Shin-Puu JENG ,  Wei-Cheng WU ,  Shang-Yun HOU ,  Chen-Hua YU ,  Tzuan-Horng LIU ,  Tzu-Wei CHIU ,  Kuo-Ching HSU

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L21/76885 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00

Abstract: The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.

Abstract translation: 上述实施例提供了在封装的集成电路（IC）芯片上用测试焊盘在金属焊盘上形成金属凸块的机构。 形成钝化层以覆盖测试焊盘和可能的金属焊盘部分。 钝化层不覆盖远离测试焊盘区域和金属焊盘区域的表面。 通过钝化层测试焊盘和金属焊盘部分的有限覆盖减少了形成在金属焊盘和金属凸块之间的UBM层的界面电阻。 这种界面电阻的降低导致金属凸块的电阻降低。