公开(公告)号：US20030213981A1

公开(公告)日：2003-11-20

申请号：US10463470

申请日：2003-06-18

Applicant: SEIKO EPSON CORPORATION

Inventor： Nobuaki Hashimoto

IPC: H01L031/0328

CPC classification number: H01L24/11 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device (150) has a semiconductor chip provided with electrodes (158), a resin layer (152) forming a stress relieving layer provided, on the semiconductor chip, wiring (154) formed from the electrodes (158) to over the resin layer (152), and solder balls (157) formed on the wiring (154) over the resin layer (152); the resin layer (152) is formed so as to have a depression (152a) in the surface, and the wiring (154) is formed so as to pass over the depression (152a).

Abstract translation: 具有接近其芯片尺寸的封装尺寸的半导体器件除了应力吸收层之外还有效地吸收热应力。 半导体器件（150）具有设置有电极（158）的半导体芯片，在半导体芯片上形成有应力消除层的树脂层（152），由电极（158）形成到布线（154）上方的树脂 层（152）和形成在所述布线（154）上的所述树脂层（152）上的焊球（157）。 树脂层（152）形成为在表面上具有凹部（152a），并且布线（154）形成为越过凹部（152a）。

公开(公告)号：US20030080425A1

公开(公告)日：2003-05-01

申请号：US10032941

申请日：2001-10-31

Inventor： Harry Hedler ,  Thorsten Meyer ,  Barbara Vasquez

IPC: H01L023/48

CPC classification number: B81B7/0048 ,  G01R31/2863 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/31 ,  H01L24/81 ,  H01L24/90 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68359 ,  H01L2224/02319 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/11003 ,  H01L2224/13099 ,  H01L2224/81801 ,  H01L2224/83194 ,  H01L2224/90 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/29099

Abstract: A semiconductor structure includes a semiconductor substrate and a compliant interconnect element disposed on a first surface of the substrate. The compliant interconnect element defines a chamber between the first surface of the substrate and a surface of the compliant interconnect element. The compliant interconnect element can be a compliant layer. The compliant layer can be formed of a polymer, such as silicone. A conductive layer can be disposed on the compliant layer, in contact with a contact pad on the semiconductor substrate. A method for forming a semiconductor structure includes providing a semiconductor substrate and providing a compliant interconnect element on a first surface of the substrate, so that the compliant interconnect element defines a chamber between the compliant interconnect element and the first surface of the substrate.

Abstract translation: 半导体结构包括半导体衬底和布置在衬底的第一表面上的柔性互连元件。 柔性互连元件在衬底的第一表面和柔性互连元件的表面之间限定腔室。 兼容互连元件可以是兼容层。 柔性层可以由聚合物形成，例如聚硅氧烷。 导电层可以设置在柔性层上，与半导体衬底上的接触焊盘接触。 一种用于形成半导体结构的方法包括提供半导体衬底并在衬底的第一表面上提供柔性互连元件，使得柔性互连元件在柔性互连元件和衬底的第一表面之间限定腔室。

公开(公告)号：US06465878B2

公开(公告)日：2002-10-15

申请号：US09777782

申请日：2001-02-06

Applicant: Joseph Fjelstad ,  Konstantine Karavakis

Inventor： Joseph Fjelstad ,  Konstantine Karavakis

IPC: H01L23495

CPC classification number: H01L23/3114 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/498 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/72 ,  H01L24/82 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/85424 ,  H01L2924/00011 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/01004

Abstract: A microelectronic assembly includes a microelectronic element having a first surface including a central region and a peripheral region surrounding the central region, the microelectronic element including a plurality of contacts disposed in the central region. The microelectronic assembly also includes a compliant layer over the peripheral region of the first surface, the compliant layer having a bottom surface facing toward the first surface of the microelectronic element, a top surface facing upwardly away from the microelectronic element and one or more edge surfaces extending between the top and bottom surfaces. A plurality of flexible bond ribbons are disposed over the compliant layer so that the bond ribbons extend over the top surface and one or more of the edge surfaces and the bond ribbons electrically connect the contacts to conductive terminals overlying the top surface of the compliant layer.

Abstract translation: 微电子组件包括具有包括中心区域和围绕中心区域的周边区域的第一表面的微电子元件，微电子元件包括设置在中心区域中的多个触点。 微电子组件还包括在第一表面的周边区域上的柔顺层，柔顺层具有面向微电子元件的第一表面的底表面，面向上远离微电子元件的顶表面和一个或多个边缘表面 在顶部和底部表面之间延伸。 多个柔性接合带设置在柔性层上方，使得接合带在顶表面上延伸，并且一个或多个边缘表面和接合带将触头电连接到覆盖顺应层的顶表面的导电端子。

公开(公告)号：US20020070440A1

公开(公告)日：2002-06-13

申请号：US09866660

申请日：2001-05-30

Applicant: Fujitsu Limited

Inventor： Yoshitaka Aiba ,  Mitsutaka Sato

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50 ,  H01L023/48 ,  H01L023/52

CPC classification number: H01L24/13 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/27436 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1067 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device is provided. The method comprises a wire-forming step of forming a wiring on a substrate having an electrode pad so as to connect the electrode pad to a mounting terminal. The wire-forming step includes the steps of: applying a metal foil to the substrate by providing an adhesive therebetween; patterning the metal foil into a predetermined pattern so as to form the wiring; and connecting the wiring to the electrode pad electrically.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在具有电极焊盘的基板上形成布线以便将电极焊盘连接到安装端子的线形成步骤。 线形成步骤包括以下步骤：通过在其间提供粘合剂将金属箔施加到基底上; 将金属箔图案化成预定图案以形成布线; 并将布线与电极焊盘电连接。

公开(公告)号：US06396145B1

公开(公告)日：2002-05-28

申请号：US09446979

申请日：1999-12-30

Applicant: Akira Nagai ,  Takumi Ueno ,  Haruo Akahoshi ,  Syuji Eguchi ,  Masahiko Ogino ,  Toshiya Satoh ,  Asao Nishimura ,  Ichiro Anjoh

Inventor： Akira Nagai ,  Takumi Ueno ,  Haruo Akahoshi ,  Syuji Eguchi ,  Masahiko Ogino ,  Toshiya Satoh ,  Asao Nishimura ,  Ichiro Anjoh

IPC: H01L2348

CPC classification number: H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02145 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/08225 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads formed on the side of the integrated circuitry formation surface of the in semiconductor element, bump electrodes for external connection electrically connected to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relaxation layer being adhered thereto, wherein more than one third of the stress relaxation layer from a surface thereof is cut away for removal and wherein the stress relaxation layer is subdivided into a plurality of regions.

Abstract translation: 半导体器件包括布置成形成集成电路的半导体元件，形成在半导体元件的集成电路形成表面侧的多个电极焊盘，用于通过导电层电连接到电极焊盘的用于外部连接的凸起电极， 以及一方面在集成电路形成表面和电极焊盘之间形成的应力松弛层，另一方面在凸起电极和导电层之间形成应力松弛层，应力松弛层粘附到其上，其中来自一个或多个应力松弛层的三分之一以上 其表面被切除以除去，并且其中应力松弛层被细分为多个区域。

公开(公告)号：US20240321790A1

公开(公告)日：2024-09-26

申请号：US18458118

申请日：2023-08-29

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Kei OBARA ,  Kazumichi TSUMURA

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05551 ,  H01L2224/05573 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13006 ,  H01L2224/13026 ,  H01L2224/13144 ,  H01L2225/06513

Abstract: A bonding-type interconnection member includes a first substrate having a first through hole extending in a first direction; a second substrate having a second through hole extending in the first direction; an interconnection portion stacked on at least one of the first substrate and the second substrate, and having a through hole continuous with the first through hole and the second through hole; a conductive film provided on a side surface of the through hole of the interconnection portion; at least two bonding metal portions positioned between the first substrate and the second substrate, and bonding the first substrate and the second substrate; and a foundation metal film provided between the bonding metal portions and the interconnection portion. The conductive film is made of a material different from a material of the bonding metal portions and a material of the foundation metal film.

公开(公告)号：US12080600B2

公开(公告)日：2024-09-03

申请号：US17010610

申请日：2020-09-02

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L21/78 ,  H01L21/4857 ,  H01L21/561 ,  H01L22/14 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/04 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05011 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05083 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05551 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/0535 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/186 ,  H01L2924/351 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/92 ,  H01L21/78 ,  H01L2224/19 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/11

Abstract: A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

公开(公告)号：US11862588B2

公开(公告)日：2024-01-02

申请号：US17323506

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Ting-Li Yang ,  Po-Hao Tsai ,  Chien-Chen Li ,  Ming-Da Cheng

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/16 ,  H01L2224/0236 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/16225

Abstract: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

公开(公告)号：US11646279B2

公开(公告)日：2023-05-09

申请号：US17184659

申请日：2021-02-25

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xiaodong Li ,  Ramasamy Chockalingam ,  Juan Boon Tan

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/0221 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/04042 ,  H01L2224/05647

Abstract: A semiconductor structure may be provided, including a conductive pad, a slot arranged through the conductive pad, a passivation layer arranged over the conductive pad and a plurality of electrical interconnects arranged under the conductive pad. The conductive pad may include an electrically conductive material and the slot may include an electrically insulating material. The passivation layer may include an opening that may expose a portion of the conductive pad and the slot may be arranged laterally between the exposed portion of the conductive pad and the plurality of electrical interconnects.

公开(公告)号：US10083926B1

公开(公告)日：2018-09-25

申请号：US15840842

申请日：2017-12-13

Applicant: Dialog Semiconductor (UK) Limited

Inventor： Ian Kent ,  Rajesh Subraya Aiyandra ,  Jesus Mennen Belonio, Jr. ,  Habeeb Mohiuddin Mohammed ,  Domingo Jr. Maggay ,  Robert Lamoon ,  Ernesto Gutierrez, III

IPC: H01L23/52 ,  H01L21/44 ,  H01L23/00

CPC classification number: H01L24/04 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/06 ,  H01L2224/03

Abstract: A wafer level chip scale package is described. At least one redistribution layer is connected to a wafer through an opening through a first polymer layer to a metal pad on a top surface of the wafer wherein the redistribution layer has a roughened top surface and wherein holes are formed through the at least one redistribution layer in an area where the redistribution layer has an area exceeding 0.2 mm2. At least one UBM layer contacts the at least one redistribution layer through an opening in a second polymer layer wherein the second polymer layer contacts the first polymer layer within the holes promoting cohesion between the first and second polymer layers and wherein the roughened top surface promotes adhesion between the at least one redistribution layer and the second polymer layer.