公开(公告)号：US20240250020A1

公开(公告)日：2024-07-25

申请号：US18602665

申请日：2024-03-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu ,  Der-Chyang Yeh ,  Ming Shih Yeh

IPC分类号： H01L23/522 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/07 ,  H01L25/075 ,  H01L33/00 ,  H01L33/06 ,  H01L33/32 ,  H01L33/38 ,  H01L33/62

CPC分类号： H01L23/5226 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/11 ,  H01L24/89 ,  H01L25/072 ,  H01L25/0753 ,  H01L33/0093 ,  H01L33/38 ,  H01L33/62 ,  H01L21/3212 ,  H01L24/81 ,  H01L33/007 ,  H01L33/06 ,  H01L33/32 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03622 ,  H01L2224/08225 ,  H01L2224/08501 ,  H01L2224/80006 ,  H01L2224/80815 ,  H01L2224/80895 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/005 ,  H01L2933/0066

摘要： A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

公开(公告)号：US11990430B2

公开(公告)日：2024-05-21

申请号：US17186742

申请日：2021-02-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Yu Tsai ,  Ku-Feng Yang ,  Wen-Chih Chiou

IPC分类号： H01L23/00

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/03013 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0355 ,  H01L2224/03612 ,  H01L2224/03622 ,  H01L2224/0381 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05546 ,  H01L2224/05564 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/2781 ,  H01L2224/27831 ,  H01L2224/29006 ,  H01L2224/29027 ,  H01L2224/29028 ,  H01L2224/32145 ,  H01L2224/32225

摘要： A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

公开(公告)号：US20240113055A1

公开(公告)日：2024-04-04

申请号：US17937429

申请日：2022-09-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Nicholas Alexander Polomoff ,  Eric Perfecto ,  Katsuyuki Sakuma ,  Mukta Ghate Farooq ,  Spyridon Skordas ,  Sathyanarayanan Raghavan ,  Michael P. Belyansky

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/08 ,  H01L24/03 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03019 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06593 ,  H01L2924/3512

摘要： A hybrid bonded semiconductor structure includes a first substrate and a second substrate each having an interface joined in a hybrid bond. Each substrate has a die portion and a crackstop structure adjacent the die portion. One or more voids in the first substrate and the second substrate are formed in or about a portion of a periphery of each crackstop structure. At least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a unified void with airgaps across the hybrid bond interface.

公开(公告)号：US20230387051A1

公开(公告)日：2023-11-30

申请号：US18446028

申请日：2023-08-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Yu Tsai ,  Ku-Feng Yang ,  Wen-Chih Chiou

IPC分类号： H01L23/00

CPC分类号： H01L24/03 ,  H01L24/29 ,  H01L24/27 ,  H01L24/05 ,  H01L2224/27831 ,  H01L2224/03622 ,  H01L2224/03013 ,  H01L2224/0381 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03612 ,  H01L2224/0355 ,  H01L2224/05084 ,  H01L2224/05083 ,  H01L2224/05546 ,  H01L2224/05564 ,  H01L2224/29006 ,  H01L2224/29028 ,  H01L2224/29027 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/2781

摘要： A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

公开(公告)号：US20230207501A1

公开(公告)日：2023-06-29

申请号：US17725413

申请日：2022-04-20

申请人： Changxin Memory Technologies, Inc.

发明人： Liang WANG ,  Qian XU

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/05008 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/04941

摘要： A semiconductor structure and a method of manufacturing the semiconductor structure are provided. The semiconductor structure includes a substrate including a plurality of pads spaced apart from each other, a first groove, and a second groove connected with the first groove, the first and the second grooves located in the substrate. The first groove is located on the side of the second groove away from the plurality of pads, and the bottom of the second groove exposes a corresponding pad of the plurality of pads. The orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate. A redistribution layer is disposed on a surface of the corresponding pad, the inner wall of the first groove, and the inner wall and the bottom of the second groove. The semiconductor structure prevents contamination or damage of test probes.

公开(公告)号：US20190252244A1

公开(公告)日：2019-08-15

申请号：US15895512

申请日：2018-02-13

申请人： Raytheon Company

发明人： Sean P. Kilcoyne ,  Eric R. Miller ,  George Grama

IPC分类号： H01L21/768 ,  H01L21/56 ,  H05K3/42 ,  C23C18/16 ,  H01L23/31 ,  H01L23/528 ,  C25D7/12

CPC分类号： H01L21/7684 ,  C23C18/1653 ,  C23C18/168 ,  C25D7/123 ,  H01L21/02065 ,  H01L21/568 ,  H01L21/76873 ,  H01L23/3121 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L2221/1089 ,  H01L2224/03009 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03845 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83896 ,  H05K3/424

摘要： A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.

公开(公告)号：US20190214356A1

公开(公告)日：2019-07-11

申请号：US16354797

申请日：2019-03-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Jung Yang ,  Hsien-Wei Chen ,  Hsien-Ming Tu ,  Chang-Pin Huang ,  Yu-Chia Lai ,  Tung-Liang Shao

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L24/02 ,  H01L21/76802 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/02311 ,  H01L2224/02351 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0346 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05563 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/73204 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00

摘要： A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

公开(公告)号：US20190006409A1

公开(公告)日：2019-01-03

申请号：US16126314

申请日：2018-09-10

申请人： Sensors Unlimited, Inc.

发明人： Namwoong Paik ,  Wei Huang

IPC分类号： H01L27/146 ,  H01L23/00

CPC分类号： H01L27/14634 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14605 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/05571 ,  H01L2224/10145 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/119 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another.

公开(公告)号：US20180211916A1

公开(公告)日：2018-07-26

申请号：US15927742

申请日：2018-03-21

申请人： Alpha and Omega Semiconductor (Cayman) Ltd.

发明人： Yan Xun Xue

IPC分类号： H01L23/535 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31 ,  H01L21/304 ,  H01L23/48 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498

CPC分类号： H01L23/535 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05025 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015

摘要： A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

公开(公告)号：US10008478B2

公开(公告)日：2018-06-26

申请号：US15326401

申请日：2015-11-24

申请人： TONGFU MICROELECTRONICS CO., LTD.

发明人： Wanchun Ding

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/11334 ,  H01L2224/1162 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00

摘要： The present disclosure discloses a fabrication method for wafer-level packaging, comprising: forming a first photoresist on a first chip and a plurality of first openings at the first photoresist to expose a functional surface of the first chip, forming an under-bump metal layer on the functional surface exposed through the plurality of first openings, and removing the first photoresist; connecting a functional solder bump of a second chip to the under-bump metal layer on the first chip; forming a filling layer between the first chip, and the second chip; and forming a connecting member on the first chip, wherein a solder ball is disposed at a top surface of the connecting member, and an apex of the solder ball is higher than a top surface of the second chip.