公开(公告)号：US20120189845A1

公开(公告)日：2012-07-26

申请号：US13437814

申请日：2012-04-02

Applicant: Sadahito MISUMI ,  Takeshi MATSUMURA

Inventor： Sadahito MISUMI ,  Takeshi MATSUMURA

IPC: C09J7/02 ,  C09J163/00 ,  B32B27/06

CPC classification number: H01L25/0657 ,  C08L33/00 ,  C08L63/00 ,  C08L2666/02 ,  C08L2666/22 ,  C09J161/06 ,  H01L21/6836 ,  H01L23/3121 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/3011 ,  Y10T156/10 ,  Y10T428/1462 ,  Y10T428/2887 ,  H01L2924/00012 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/20752

Abstract: Provided are a semiconductor device producing method with simple production steps while preventing contamination of a bonding pad and preventing warp generation in an adherend such as a substrate, a lead frame, or a semiconductor element, thereby improving yield; an adhesive sheet used in this method; and a semiconductor device obtained by this method. The invention includes a pre-setting step of pre-setting a semiconductor element 13 to an adherend 11 through an adhesive sheet 12, and a wire bonding step of wire bonding the element 13 in the bonding temperatures range of 80 to 250° C. without performing any heating step, wherein, as the adhesive sheet 12, a sheet having a storage elastic modulus of 1 MPa or more in the temperature range of 80 to 250° C. or a storage elastic modulus of 11 MPa or more at any temperature in the temperature range before curing the sheet 12 is used.

Abstract translation: 提供一种半导体器件制造方法，其具有简单的制造步骤，同时防止焊盘的污染并防止诸如衬底，引线框架或半导体元件的被粘物中的翘曲产生，从而提高产量; 在该方法中使用的粘合片; 以及通过该方法获得的半导体器件。 本发明包括通过粘合片12将半导体元件13预先设置到被粘物11的预设步骤，以及在80至250℃的接合温度范围内将元件13引线接合的引线接合步骤，而没有 进行任何加热步骤，其中，作为粘合片12，在80〜250℃的温度范围内具有1MPa以上的储能弹性模量或在任何温度下的储能弹性模量为11MPa以上的片材 使用固化片材12之前的温度范围。

公开(公告)号：US08159057B2

公开(公告)日：2012-04-17

申请号：US12423826

申请日：2009-04-15

Applicant: Mikako Okada ,  Toshikazu Ishikawa

Inventor： Mikako Okada ,  Toshikazu Ishikawa

IPC: H01L23/06

CPC classification number: H01L23/50 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15183 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/85186 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/4554

Abstract: The mounting height of a semiconductor device is reduced. A wiring substrate has an upper surface with multiple bonding leads formed therein and a lower surface with multiple lands formed therein. This wiring substrate is a multilayer wiring substrate and multiple wiring layers and multiple insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper surface side and on the lower surface side of the core material. The third insulating layers are formed on the upper surface side and on the lower surface side of the core material with the second insulating layers in-between. The uppermost wiring layer and the lowermost wiring layer are formed over the third insulating layers.

Abstract translation: 降低了半导体器件的安装高度。 布线基板具有形成在其中的多个接合引线的上表面和形成有多个焊盘的下表面。 该布线基板是多层布线基板，并且在布线基板的芯材的上表面侧和下表面侧交替形成多个布线层和多​​个绝缘层。 接合引线由最上层布线层的一部分形成，焊盘由最下层布线层的一部分形成。 绝缘层包括含有纤维和树脂的第二绝缘层和比第二绝缘层小的纤维含量的第三绝缘层。 第二绝缘层形成在芯材的上表面侧和下表面侧上。 第三绝缘层形成在芯材的上表面侧和下表面侧，其间具有第二绝缘层。 最上面的布线层和最下面的布线层形成在第三绝缘层上。

公开(公告)号：US08120167B2

公开(公告)日：2012-02-21

申请号：US12904314

申请日：2010-10-14

Applicant: David R. Hembree ,  Alan G. Wood

Inventor： David R. Hembree ,  Alan G. Wood

IPC: H01L23/00

CPC classification number: H01L24/16 ,  G01R1/06716 ,  G01R1/07307 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02125 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/0333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/45116 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45655 ,  H01L2224/45684 ,  H01L2224/45698 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48455 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/4899 ,  H01L2224/48992 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/10155 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45164 ,  H01L2924/013 ,  H01L2924/00013

Abstract: A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.

Abstract translation: 一种用封装的直通线互连制造半导体部件的方法包括以下步骤：提供具有第一面，第二面和基板接触的基板; 在基板接触中形成通孔，将基板形成到第二面; 将电线放置在通孔中; 在靠近第一侧的导线上形成第一触点，并且在靠近第二侧的导线上形成第二触点; 并在第一侧上形成聚合物层，留下暴露的第一接触。 聚合物层可以使用薄膜辅助成型方法形成，包括以下步骤：在粘合部件的顶端部分上形成模具膜，模制聚合物层，然后移除模具膜以暴露粘合部件的末端部分。 通线互连提供了在半导体衬底的相对侧上具有触点的多电平互连。

公开(公告)号：US20120025384A1

公开(公告)日：2012-02-02

申请号：US13267385

申请日：2011-10-06

Applicant: Khalil Hosseini ,  Matthias Stecher

Inventor： Khalil Hosseini ,  Matthias Stecher

IPC: H01L23/52 ,  H01L21/50

CPC classification number: H01L24/48 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/0347 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73257 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2224/05164 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/2075 ,  H01L2924/00012 ,  H01L2924/01006

Abstract: An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer.

Abstract translation: 公开了一种用于生产的电子设备和方法。 一个实施例提供了一种集成部件，其具有由铜或铜合金构成的第一层或者包含铜或铜合金的第一层，并且具有导电的第二层，其材料与第一层的材料不同， 设置在第一层和第二层上。

公开(公告)号：US20120006882A1

公开(公告)日：2012-01-12

申请号：US13063852

申请日：2010-03-26

Applicant: Gary S. Gillotti

Inventor： Gary S. Gillotti

IPC: B23K31/02 ,  B23K20/10

CPC classification number: H01L24/85 ,  B23K3/0623 ,  B23K20/004 ,  B23K2101/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/1134 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13664 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/78301 ,  H01L2224/78801 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/851 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  Y10S228/904 ,  H01L2224/85186 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/01006 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method of forming a conductive bump is provided. The method includes the steps of: (1) bonding a free air ball to a bonding location using a bonding tool to form a bonded ball; (2) raising the bonding tool to a desired height, with a wire clamp open, while paying out wire continuous with the bonded ball; (3) closing the wire clamp; (4) lowering the bonding tool to a smoothing height with the wire clamp still closed; (5) smoothing an upper surface of the bonded ball, with the wire clamp still closed, using the bonding tool; and (6) raising the bonding tool, with the wire clamp still closed, to separate the bonded ball from wire engaged with the bonding tool.

Abstract translation: 提供一种形成导电凸块的方法。 该方法包括以下步骤：（1）使用接合工具将自由空气球结合到接合位置以形成接合球; （2）将焊接工具提升到所需的高度，同时将电线夹打开，同时支付与接合球连续的电线; （3）关闭线夹; （4）将导线夹仍然封闭时，将焊接工具降至平滑高度; （5）使用焊接工具使焊丝夹仍然闭合，使接合球的上表面平滑化; 和（6）提升接合工具，线夹仍然闭合，以将接合球与接合工具接合的线分离。

公开(公告)号：US08053351B2

公开(公告)日：2011-11-08

申请号：US12903714

申请日：2010-10-13

Applicant: Hwang-Bok Ryu ,  Ky-Hyun Jung ,  Jae-Yong Park ,  Ho-Geon Song

Inventor： Hwang-Bok Ryu ,  Ky-Hyun Jung ,  Jae-Yong Park ,  Ho-Geon Song

IPC: H01L21/60

CPC classification number: H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48599 ,  H01L2224/49 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method of forming at least one bonding structure may be provided. A ball may be formed on the front end of a wire outside a capillary. The capillary may be moved downwardly to form a preliminary compressed ball on a first pad using the ball. The capillary may be moved upwardly to form a neck portion on the preliminary compressed ball using the preliminary compressed ball and the wire. The capillary may be moved obliquely and downwardly to form a compressed ball. The capillary may extend the wire from the compressed ball to a second pad.

Abstract translation: 可以提供形成至少一个结合结构的方法。 可以在毛细管外部的线的前端形成球。 毛细管可以向下移动以在使用球的第一垫上形成预压缩球。 毛细管可以向上移动，以便在预压缩球上形成颈部，使用预压缩球和线。 毛细管可以倾斜向下移动以形成压缩球。 毛细管可以将丝线从压缩球延伸到第二垫。

公开(公告)号：US08039970B2

公开(公告)日：2011-10-18

申请号：US12021780

申请日：2008-01-29

Applicant: Kazuhiro Yamamori ,  Katsuhiro Ishida

Inventor： Kazuhiro Yamamori ,  Katsuhiro Ishida

IPC: H01L23/49

CPC classification number: H01L24/85 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/8385 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A stacked semiconductor device includes a first semiconductor element mounted on a circuit substrate and a second semiconductor element stacked on the first semiconductor element via a spacer layer. An electrode pad of the first semiconductor element is electrically connected to a connection portion of the circuit substrate through a first metal wire. A vicinity of the end portion of the first metal wire connected to the electrode pad is in contact with an insulating protection film which covers the surface of the first semiconductor element.

Abstract translation: 层叠半导体器件包括安装在电路基板上的第一半导体元件和经由间隔层堆叠在第一半导体元件上的第二半导体元件。 第一半导体元件的电极焊盘通过第一金属线电连接到电路基板的连接部分。 连接到电极焊盘的第一金属线的端部附近与覆盖第一半导体元件的表面的绝缘保护膜接触。

公开(公告)号：US20110199737A1

公开(公告)日：2011-08-18

申请号：US13097465

申请日：2011-04-29

Applicant: Katsuyuki Yonehara

Inventor： Katsuyuki Yonehara

IPC: H05K7/00

CPC classification number: H01L23/13 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor package which includes: a semiconductor chip to which one end of each of a plurality of wires is connected; and a board on which the semiconductor chip is fixed, and a plurality of board wires to which the plurality of corresponding wires are connected are disposed, wherein the board includes: a first wiring pair that includes a first pair of wires in parallel with each other and first two board wires connected to the corresponding wires, one of the wires connected to one of the board wires crossing the other board wire without contact with the other board wire, and a second wiring pair that is provided adjacent to the first wiring pair and includes a second pair of wires in parallel with each other and second two board wires connected to the corresponding wires without a crossing.

Abstract translation: 本发明的实施例提供一种半导体封装，其包括：连接有多条电线的一端的半导体芯片; 以及其上固定有半导体芯片的板，并且布置有多个相应的导线连接到的多个板布线，其中所述板包括：第一布线对，其包括彼此平行的第一对布线 以及连接到相应导线的前两个电路板线，其中一个电线连接到与另一个电路板电线交叉的一个电路板电线，而不与另一个电路板接线接触;以及第二配线对，其设置成与第一配线对相邻， 包括彼此平行的第二对电线和连接到相应电线而没有交叉的第二两个电路板电线。

公开(公告)号：US20110199473A1

公开(公告)日：2011-08-18

申请号：US13024373

申请日：2011-02-10

Applicant: Kazuaki KOJIMA

Inventor： Kazuaki KOJIMA

IPC: H04N7/18 ,  H01L23/48

CPC classification number: H04N7/183 ,  A61B1/05 ,  H01L23/4985 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An image pickup apparatus according to an embodiment includes: an image pickup device chip including an image pickup device formed on a first principal surface thereof and an external terminal for the image pickup device formed on a second principal surface thereof; a wiring board including a distal end portion including a connection pad, a flexure portion flexed at an angle of no less than 90 degrees, and an extending portion, the wiring board including a wiring layer extending from the distal end portion to the extending portion via the flexure portion, the wiring board being kept within a space immediately above the second principal surface of the image pickup device chip; a bonding layer that joins the second principal surface of the image pickup device chip and the distal end portion of the wiring board; and a bonding wire that electrically connects the external terminal and the connection pad.

Abstract translation: 根据实施例的图像拾取装置包括：图像拾取装置芯片，包括形成在其第一主表面上的图像拾取装置和形成在其第二主表面上的图像拾取装置的外部端子; 布线基板，包括：包括连接焊盘的远端部分，弯曲角度不小于90度的挠曲部分和延伸部分，所述布线板包括从所述远端部分延伸到所述延伸部分的布线层 挠曲部分，布线板保持在图像拾取装置芯片的第二主表面之上的空间内; 连接图像拾取器件芯片的第二主表面和布线板的远端部分的接合层; 以及将外部端子和连接焊盘电连接的接合线。

公开(公告)号：US07998552B2

公开(公告)日：2011-08-16

申请号：US12529070

申请日：2008-01-28

Applicant: Yasuhiro Amano ,  Sadahito Misumi ,  Takeshi Matsumura

Inventor： Yasuhiro Amano ,  Sadahito Misumi ,  Takeshi Matsumura

IPC: H01L21/301 ,  H01L21/52

CPC classification number: H01L23/3121 ,  C08G18/4045 ,  C08G18/6254 ,  C08L33/08 ,  C09J175/04 ,  H01L21/6836 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/27436 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29316 ,  H01L2224/29318 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29371 ,  H01L2224/29386 ,  H01L2224/29393 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/8388 ,  H01L2224/83885 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10T428/24355 ,  H01L2924/00014 ,  H01L2924/0635 ,  H01L2924/066 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2924/05432 ,  H01L2924/0532 ,  H01L2924/04642 ,  H01L2924/05042 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: A dicing die-bonding film in which the adhesive properties during the dicing step and the peeling properties during the pickup step are controlled so that both become good, and a production method thereof, are provided. The dicing die-bonding film in the present invention is a dicing die-bonding film having a pressure-sensitive adhesive layer on a base material and a die bond layer on the pressure-sensitive adhesive layer, in which the arithmetic mean roughness X (μm) on the pressure-sensitive adhesive layer side in the die bond layer is 0.015 μm to 1 μm, the arithmetic mean roughness Y (μm) on the die bond layer side in the pressure-sensitive adhesive layer is 0.03 μm to 1 μm, and the absolute value of the difference of the X and Y is 0.015 or more.

Abstract translation: 控制在切割步骤期间的粘合性能和拾取步骤期间的剥离性能使得两者都变得良好的切割芯片接合膜及其制备方法。 本发明的切割/芯片接合薄膜是在基材上具有压敏粘合剂层和压敏粘合剂层上的芯片接合层的切割芯片接合薄膜，其中算术平均粗糙度X（μm ）为0.015μm〜1μm，压敏粘合剂层的芯片接合层侧的算术平均粗糙度Y（μm）为0.03μm〜1μm， X和Y的差的绝对值为0.015以上。