公开(公告)号：US08741766B2

公开(公告)日：2014-06-03

申请号：US13905845

申请日：2013-05-30

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/48

CPC classification number: H01L24/14 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.

Abstract translation: 半导体器件具有具有管芯凸块焊盘的半导体管芯和具有集成凸块焊盘的迹线的衬底。 在芯片凸块焊盘或集成凸块焊盘之间间隙地形成焊接掩模贴片。 焊接掩模贴片包含不可润湿的材料。 导电凸块材料沉积在集成的凸块焊盘或模具凸块焊盘上。 半导体管芯安装在衬底上，使得导电凸块材料设置在管芯凸块焊盘和集成凸块焊盘之间。 凸块材料在集成的凸块焊盘周围没有焊接掩模的情况下回流以形成半导体管芯和衬底之间的互连。 焊接掩模贴片将导电凸块材料限制在回流焊中芯片凸块焊盘或集成凸块焊盘的占位面积内。 互连可以具有不可熔的基底和易熔盖。

公开(公告)号：US20140145340A1

公开(公告)日：2014-05-29

申请号：US14170295

申请日：2014-01-31

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/522 ,  H01L21/76838 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/16 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1411 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17107 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/325 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/3512

Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract translation: 通过机械地互锁第一和第二元件的接合表面来形成倒装芯片互连结构。 可以是集成电路芯片上的凸起的第一元件包括具有低屈服强度和高伸长率的软的可变形的材料。 第二元件的表面（其可以例如是衬底）具有凹凸，第一元件在压力下塑性变形，以形成机械互锁。

公开(公告)号：US08729687B2

公开(公告)日：2014-05-20

申请号：US13649834

申请日：2012-10-11

Applicant: STATS ChipPAC Ltd.

Inventor： Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/31 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/315 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/48227 ,  H01L2224/48479 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/48471 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Abstract translation: 提供了一种堆叠集成电路封装包装系统，包括形成第一外部互连; 在第一外部互连下方安装第一集成电路管芯; 在第一集成电路管芯上以不在第一外部互连上的偏移配置堆叠第二集成电路管芯; 将所述第一集成电路管芯与所述第一外部互连件连接; 并且将所述第二集成电路管芯与所述第一外部互连件封装，并且所述第一集成电路管芯部分地露出。

公开(公告)号：US08709935B2

公开(公告)日：2014-04-29

申请号：US13768862

申请日：2013-02-15

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  OhHan Kim ,  SungWon Cho

IPC: H01L21/44 ,  H01L21/50 ,  H01L23/52 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L23/522 ,  H01L21/565 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电焊盘。 通过在第一导电焊盘中形成多个凹槽来扩展第一导电焊盘的互连表面积。 凹槽可以是同心环的布置，圆形凹槽的布置或平行的线性沟槽的布置。 或者，通过在第一导电焊盘上形成第二导电焊盘来扩展第一导电焊盘的互连表面积。 半导体管芯具有形成在半导体管芯的表面上的多个互连结构。 半导体管芯安装到衬底上，互连结构接触第一导电焊盘的扩展互连表面区域，以增加互连结构与第一导电焊盘的接合强度。 模具底部填充材料沉积在半导体管芯和衬底之间。

公开(公告)号：US20140110861A1

公开(公告)日：2014-04-24

申请号：US14143891

申请日：2013-12-30

Applicant: STATS ChipPAC, Ltd

Inventor： Nathapong Suthiwongsunthorn ,  Pandi C. Marimuthu ,  Jae Hun Ku ,  Glenn Omandam ,  Hin Hwa Goh ,  Kock Liang Heng ,  Jose A. Caparas

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

Abstract translation: 半导体器件包括衬底和延伸穿过衬底的通孔。 第一绝缘层设置在通孔的侧壁上。 在第一绝缘层上的通孔中设置导电材料以形成TSV。 第一互连结构设置在衬底的第一侧上。 半导体管芯或部件安装到第一互连结构。 密封剂设置在第一互连结构和半导体管芯或部件上。 第二互连结构设置在衬底的第二侧上。 第二互连结构电连接到TSV。 第二互连结构包括设置在衬底的第二表面上的第二绝缘层和TSV，以及设置在TSV上方并通过第二绝缘层与TSV接触的第一导电层。

公开(公告)号：US20140103527A1

公开(公告)日：2014-04-17

申请号：US14135415

申请日：2013-12-19

Applicant: STATS ChipPAC, Ltd.

Inventor： Pandi C. Marimuthu ,  Yaojian Lin ,  Kang Chen ,  Yu Gu ,  Won Kyoung Choi

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/24101 ,  H01L2224/24155 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81125 ,  H01L2224/81127 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/82 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/92 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/207 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2224/45099

Abstract: A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.

Abstract translation: 半导体器件具有基板。 通过衬底形成多个导电通孔。 导电层形成在衬底上。 在导电层上形成绝缘层。 去除衬底的一部分以暴露导电通孔。 在衬底上形成多个垂直互连结构。 第一半导体管芯设置在衬底上。 垂直互连结构的高度小于第一半导体管芯的高度。 密封剂沉积在第一半导体管芯和垂直互连结构之上。 密封剂的第一部分从第一半导体管芯上方移除，同时将密封剂的第二部分留在垂直互连结构上。 去除密封剂的第二部分以暴露垂直互连结构。 第二半导体管芯设置在第一半导体管芯上。

公开(公告)号：US20140077361A1

公开(公告)日：2014-03-20

申请号：US13832118

申请日：2013-03-15

Applicant: STATS CHIPPAC, LTD.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L21/66 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L22/32 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber.

Abstract translation: 半导体器件具有形成在载体上的第一互连结构。 在测试第一互连结构之后，将半导体管芯设置在第一互连结构上以使其已知良好。 半导体芯片在一个已知的好的芯片中。 在第一互连结构上形成垂直互连结构，例如凸块或凸块凸块。 分立半导体器件设置在第一互连结构或第二互连结构上。 密封剂沉积在半导体管芯，第一互连结构和垂直互连结构之上。 去除一部分密封剂以露出垂直互连结构。 第二互连结构形成在密封剂上并电连接到垂直互连结构。 第一互连结构或第二互连结构包括具有嵌入的玻璃布，玻璃交叉，填充物或纤维的绝缘层。

公开(公告)号：US20140077344A1

公开(公告)日：2014-03-20

申请号：US14087653

申请日：2013-11-22

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  DaeSik Choi ,  Jun Mo Koo

IPC: H01L23/552 ,  H01L23/34 ,  H01L23/522

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/34 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/19 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.

Abstract translation: 半导体晶片具有多个第一半导体管芯。 第二半导体管芯安装到第一半导体管芯。 在第一和第二半导体管芯之间形成屏蔽层。 在第一和第二半导体管芯之间形成诸如导电柱，凸起或接合线的电互连。 可以通过第一和第二半导体管芯形成导电TSV。 密封剂沉积在第一和第二半导体管芯和电互连上。 在第二半导体管芯上形成散热器。 可以在第二半导体管芯上形成诸如凸块的互连结构。 去除第一半导体管芯的背面的一部分。 在第一半导体管芯的暴露表面上形成保护层。 保护层覆盖第一半导体管芯的暴露的背面和侧壁。

公开(公告)号：US20140061944A1

公开(公告)日：2014-03-06

申请号：US14079273

申请日：2013-11-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jose Alvin Caparas ,  Glenn Omandam

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/315 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device.

Abstract translation: 半导体器件具有安装到载体上的半导体管芯。 第一密封剂沉积在半导体管芯和载体上。 加强支撑构件可以设置在半导体管芯周围的载体上。 在第一密封剂中形成多个通道或凹槽。 可以通过去除第一密封剂的一部分来形成凹部。 或者，凹部形成在具有多个延伸表面的追逐模具中。 可以将第二密封剂沉积到第一密封剂的凹部中。 移除载体并且在半导体管芯和第一密封剂上形成互连结构。 第一密封剂的厚度提供足够的刚度以减少翘曲，同时凹槽在形成互连结构期间提供应力释放。 去除第一密封剂和凹部的一部分以减小半导体器件的厚度。

公开(公告)号：US20140048906A1

公开(公告)日：2014-02-20

申请号：US14061244

申请日：2013-10-23

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/24155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

Abstract translation: 半导体器件具有设置在半导体封装之上的半导体封装和插入器。 半导体封装具有设置在第一半导体管芯周围的周边区域中的第一半导体管芯和模块化互连单元。 第二半导体管芯设置在与半导体封装件相对的插入件上。 在插入器和模块化互连单元之间形成互连结构。 互连结构是导电柱或螺柱凸块。 模块化互连单元具有芯基板和通过芯基板形成的多个垂直互连。 在第一半导体管芯和模块化互连单元上形成堆积互连结构。 模块化互连单元的垂直互连通过激光直接消融来暴露。 在内插器和半导体封装之间沉积底部填充物。 半导体封装和堆积互连结构的总厚度小于0.4毫米。