公开(公告)号：US09997428B2

公开(公告)日：2018-06-12

申请号：US14799534

申请日：2015-07-14

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Marshall Maple ,  Ashish Alawani ,  Li Sun ,  Sarah Haney

IPC: H01L23/367 ,  H01L21/768 ,  H01L21/48 ,  H01L29/20 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H01L29/778 ,  H01L29/737 ,  H05K3/46 ,  H01L23/373

CPC classification number: H01L23/367 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76816 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/49827 ,  H01L29/20 ,  H01L29/737 ,  H01L29/778 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1037 ,  H01L2924/13051 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/15313 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/113 ,  H05K3/0026 ,  H05K3/4644 ,  H05K2201/09509

Abstract: An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a substrate, pluralities of vias disposed in the substrate. The vias are disposed in a hexagonal arrangement.

公开(公告)号：US20180146550A1

公开(公告)日：2018-05-24

申请号：US15557438

申请日：2016-03-11

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： Markus MAIER

IPC: H05K1/05 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H05K3/44

CPC classification number: H05K1/05 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/053 ,  H05K1/056 ,  H05K1/115 ,  H05K3/4038 ,  H05K3/445 ,  H05K3/46 ,  H05K3/4608 ,  H05K2201/09509 ,  H05K2201/09554

Abstract: A printed circuit board is provided which comprises a core layer of a conductive metal having a thickness between 30 micrometer and 120 micrometer, an upper dielectric layer and a lower dielectric layer sandwiching the core layer; an upper conductive layer arranged above the upper dielectric layer and a lower conductive layer arranged below the lower dielectric layer; at least one via passing from the upper conductive layer to the lower conductive layer and filled at least partially with the dielectric material of the upper and/or lower dielectric layer; and at least one and blind via, connecting the upper conductive layer with the core layer.

公开(公告)号：US09980386B1

公开(公告)日：2018-05-22

申请号：US15795198

申请日：2017-10-26

Applicant: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd. ,  Avary Holding (Shenzhen) Co., Limited.

Inventor： Yan-Lu Li ,  Jun-Hua Wang

IPC: H05K1/18 ,  H05K3/40 ,  H05K3/46 ,  H05K1/11 ,  H05K1/03 ,  H05K3/42

CPC classification number: H05K1/183 ,  H05K1/0393 ,  H05K1/111 ,  H05K1/115 ,  H05K1/189 ,  H05K3/4069 ,  H05K3/423 ,  H05K3/462 ,  H05K3/4697 ,  H05K2201/09509

Abstract: A method for manufacturing a flexible printed circuit board includes providing a first double-sided circuit substrate which comprises an electronic component. A multilayer circuit substrate having a mounting groove is also provided. The multilayer circuit substrate covers the first double-sided circuit substrate through an adhesive layer, causing the electronic component to be received in the mounting groove, thereby forming an intermediate product. At least one through hole is defined in the intermediate product, which when filled with conductive material electrically connects the multilayer circuit substrate to the first double-sided circuit substrate to form the flexible printed circuit board.

公开(公告)号：US09961784B2

公开(公告)日：2018-05-01

申请号：US15475134

申请日：2017-03-31

Applicant: Subtron Technology Co., Ltd.

Inventor： Tzu-Wei Huang

IPC: H05K3/46 ,  H05K3/42 ,  H05K3/00 ,  H05K3/02 ,  H05K1/11 ,  B23K11/11 ,  B32B37/02 ,  B32B37/04 ,  B32B38/10 ,  B32B38/04 ,  B32B37/00 ,  B23K101/42

CPC classification number: H05K3/4682 ,  B23K11/11 ,  B23K2101/42 ,  B32B37/0084 ,  B32B37/02 ,  B32B37/04 ,  B32B38/04 ,  B32B38/10 ,  B32B2038/047 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2311/00 ,  B32B2311/12 ,  B32B2457/00 ,  B32B2457/08 ,  H05K1/115 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/02 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/46 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/09918 ,  H05K2203/1536 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.

公开(公告)号：US09844131B2

公开(公告)日：2017-12-12

申请号：US15284510

申请日：2016-10-03

Applicant: UNIFLEX Technology Inc.

Inventor： Yi-Chun Liu ,  Chiu-Pei Huang ,  Pei-Hao Hung ,  Yuan-Chih Lee

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/06 ,  H05K3/46

CPC classification number: H05K1/0278 ,  H05K1/115 ,  H05K3/064 ,  H05K3/421 ,  H05K3/423 ,  H05K3/429 ,  H05K3/4652 ,  H05K3/4664 ,  H05K3/4691 ,  H05K2201/0195 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2203/0502

Abstract: A rigid-flex circuit board includes a flexible circuit board, a plurality of patterned photo-imageable substrates and a plurality of patterned circuit layers. The flexible circuit board includes a plurality of exposed regions, a top surface and a bottom surface opposite to the top surface. The exposed regions are respectively located at the top surface and the bottom surface. The patterned photo-imageable substrates are disposed on the top surface and the bottom surface respectively. Each patterned photo-imageable substrate includes an opening exposing the corresponding exposed region. Each patterned photo-imageable substrate includes photo-sensitive material. The patterned circuit layers are disposed on the patterned photo-imageable substrates respectively and expose the exposed regions. A manufacturing method of the rigid-flex circuit board is also provided.

公开(公告)号：US09839124B2

公开(公告)日：2017-12-05

申请号：US15015551

申请日：2016-02-04

Applicant: JX NIPPON MINING & METALS CORPORATION

Inventor： Michiya Kohiki

IPC: H05K1/09 ,  H05K3/00 ,  C25D1/04 ,  H05K3/20 ,  C25D7/06 ,  H05K3/02 ,  H05K3/40 ,  H05K3/42 ,  C25D3/04 ,  C25D3/18 ,  C25D3/38 ,  C25D3/56 ,  C25D5/14 ,  C23C18/16

CPC classification number: H05K1/09 ,  C23C18/1653 ,  C25D1/04 ,  C25D3/04 ,  C25D3/18 ,  C25D3/38 ,  C25D3/562 ,  C25D5/14 ,  C25D7/0614 ,  H05K3/0058 ,  H05K3/025 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/421 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K2203/0726

Abstract: Provided is a copper foil provided with a carrier in which the laser hole-opening properties of the ultrathin copper layer are good and which is suitable for producing a high-density integrated circuit substrate. A copper foil provided with a carrier having, in order, a carrier, an intermediate layer, and an ultrathin copper layer, wherein the specular gloss at 60° in an MD direction of the intermediate layer side surface of the ultrathin copper layer is 140 or less.

公开(公告)号：US09837736B2

公开(公告)日：2017-12-05

申请号：US14311293

申请日：2014-06-21

Applicant: Keysight Technologies, Inc.

Inventor： Kuen Yew Lam ,  Thiam Ping Oon ,  Jared Richard

IPC: H05K7/00 ,  H01R12/58 ,  H05K1/11 ,  H05K7/14 ,  H05K1/16

CPC classification number: H01R12/585 ,  H05K1/115 ,  H05K1/162 ,  H05K7/1452 ,  H05K2201/044 ,  H05K2201/09509 ,  H05K2201/1059 ,  Y10T29/49128 ,  Y10T29/51 ,  Y10T156/1057

Abstract: An apparatus comprises a printed circuit board (PCB) having a first surface and a second surface, a plurality of blind press-fit vias penetrating the first surface and extending partially through the PCB toward the second surface, the blind press-fit vias configured to receive press-fit connectors of at least one component to be connected to the PCB, and a plurality of electrical connectors disposed in a region of the second surface opposite the blind press-fit vias and configured to interface with one or more signal processing components disposed on the second surface.

公开(公告)号：US20170118837A1

公开(公告)日：2017-04-27

申请号：US15311601

申请日：2015-05-12

Applicant: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.

Inventor： Kousuke MIURA ,  Satoshi KIYA ,  Sumito UEHARA

IPC: H05K1/11 ,  H05K3/46 ,  H05K1/09 ,  H05K3/40 ,  H05K1/03

CPC classification number: H05K1/115 ,  H05K1/0313 ,  H05K1/034 ,  H05K1/09 ,  H05K3/381 ,  H05K3/4084 ,  H05K3/423 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4661 ,  H05K2201/09509 ,  H05K2203/072

Abstract: An object of the present invention is to provide a printed wiring board in which conductive layers formed on two surfaces of a base layer that contains a fluororesin as a main component are reliably connected to each other through a via-hole. A printed wiring board according to an embodiment of the present invention includes a base layer containing a fluororesin as a main component, a first conductive layer stacked on one surface of the base layer, a second conductive layer stacked on the other surface of the base layer, and a via-hole that is formed along a connection hole penetrating the base layer and at least one of the first conductive layer and the second conductive layer in a thickness direction and that electrically connects the first conductive layer and the second conductive layer to each other. At least a part of an inner circumferential surface of the base layer in the connection hole has a pre-treated surface having a content ratio of oxygen atoms or nitrogen atoms of 0.2 atomic percent or more.

公开(公告)号：US20170103249A1

公开(公告)日：2017-04-13

申请号：US15286803

申请日：2016-10-06

Applicant: CORNING INCORPORATED

Inventor： Yuhui Jin ,  Matthew Evan Wilhelm

IPC: G06K9/00 ,  C03C15/00 ,  H05K3/00 ,  H05K3/40 ,  B23K26/53 ,  H05K3/22 ,  H05K1/11 ,  H05K5/00 ,  B23K26/00 ,  C03C23/00 ,  H05K1/03

CPC classification number: G06K9/00013 ,  B23K26/0006 ,  B23K26/382 ,  B23K26/386 ,  B23K26/389 ,  B23K26/402 ,  B23K26/53 ,  B23K2101/42 ,  B23K2103/54 ,  C03B33/0222 ,  C03C15/00 ,  C03C17/36 ,  C03C17/3649 ,  C03C17/3668 ,  C03C21/002 ,  C03C23/0025 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/002 ,  H05K3/0029 ,  H05K3/22 ,  H05K3/4038 ,  H05K5/0017 ,  H05K2201/09509 ,  H05K2201/10151

Abstract: A glass sensor substrate including metallizable through vias and related process is provided. The glass substrate has a first major surface, a second major surface and an average thickness of greater than 0.3 mm. A plurality of etch paths are created through the glass substrate by directing a laser at the substrate in a predetermined pattern. A plurality of through vias through the glass substrate are etched along the etch paths using a hydroxide based etching material. The hydroxide based etching material highly preferentially etches the substrate along the etch path. Each of the plurality of through vias is long compared to their diameter for example such that a ratio of the thickness of the glass substrate to a maximum diameter of each of the through vias is greater than 8 to 1.

公开(公告)号：US09559029B2

公开(公告)日：2017-01-31

申请号：US14523556

申请日：2014-10-24

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L21/44 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H05K1/18 ,  H01L25/16 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/50 ,  H05K3/46

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract translation: 半导体器件具有形成在半导体晶片的有源表面上的保护层。 具有预先施加的保护层的半导体管芯从半导体晶片移动并安装在载体上。 载体上的半导体管芯和接触焊盘被封装。 载体被移除。 在预先施加的保护层和接触垫上形成第一绝缘层。 在第一绝缘层和预先施加的保护层中形成通孔以暴露半导体管芯上的互连部位。 在第一绝缘层上形成互连结构，与半导体管芯和接触焊盘上的互连部位电接触。 互连结构具有形成在第一绝缘层上的再分布层，形成在再分配层上的第二绝缘层和形成在与再分布层电接触的第二电介质上的凸块下金属化层。