公开(公告)号：US20160043047A1

公开(公告)日：2016-02-11

申请号：US14814906

申请日：2015-07-31

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Sze Ping Goh ,  Jose A. Caparas

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/24155 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.

Abstract translation: 半导体器件包括包括导电层的第一半导体封装。 包括互连结构的衬底设置在导电层上。 具有第一半导体封装的导电层的衬底的互连结构是自对准的。 在基板上形成多个开口。 粘合剂设置在基板和第一半导体封装之间以及基板的开口中。 在与衬底相对的第一半导体封装件上方形成再分配层（RDL）。 衬底的间距与RDL的间距不同。 粘合剂延伸到基底的互连结构。 第二半导体封装设置在衬底和第一半导体封装之上。

公开(公告)号：US09252130B2

公开(公告)日：2016-02-02

申请号：US13853810

申请日：2013-03-29

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungMoon Kim ,  YoungChul Kim ,  HunTeak Lee ,  KeonTaek Kang ,  HeeJo Chi

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/81805 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods of producing a semiconductor package using dual-sided thermal compression bonding includes providing a substrate having an upper surface and a lower surface. A first device having a first surface and a second surface can be provided along with a second device having a third surface and a fourth surface. The first surface of the first device can be coupled to the upper surface of the substrate while the third surface of the second device can be coupled to the lower surface of the substrate, the coupling occurring simultaneously to produce the semiconductor package.

Abstract translation: 使用双面热压接的半导体封装的制造方法包括提供具有上表面和下表面的基板。 具有第一表面和第二表面的第一装置可以与具有第三表面和第四表面的第二装置一起提供。 第一器件的第一表面可以耦合到衬底的上表面，而第二器件的第三表面可以耦合到衬底的下表面，耦合同时发生以产生半导体封装。

公开(公告)号：US09252093B2

公开(公告)日：2016-02-02

申请号：US14084745

申请日：2013-11-20

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  JoonYoung Choi ,  Wonll Kwon

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05186 ,  H01L2224/0519 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00

Abstract: A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.

Abstract translation: 半导体晶片具有接触垫。 在晶片上形成第一绝缘层。 在第一绝缘层和接触垫上形成第二绝缘层。 去除第二绝缘层的一部分以露出接触垫。 第一UBM层形成在第二绝缘层和接触垫的轮廓之上并且跟随第二绝缘层和接触垫的轮廓以在接触垫上产生良好的孔。 在第一UBM层和接触垫上的阱中形成第一缓冲层。 在第一UBM层和第一缓冲层上形成第二UBM层。 在第二UBM层上形成第三UBM层。 在第三UBM层上形成凸块。 第一个缓冲层减少了凸块和接触垫上的应力。 可以在第二和第三UBM层之间形成第二缓冲层。

公开(公告)号：US09240331B2

公开(公告)日：2016-01-19

申请号：US14039418

申请日：2013-09-27

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungMoon Kim ,  KooHong Lee ,  JaeHak Yee ,  YoungChul Kim ,  Lan Hoang ,  Pandi C. Marimuthu ,  Steve Anderson ,  See Chian Lim ,  HeeJo Chi

IPC: H01L23/52 ,  H01L29/40 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/4867 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/10165 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13316 ,  H01L2224/13324 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13794 ,  H01L2224/138 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1701 ,  H01L2224/17517 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81007 ,  H01L2224/81011 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/8114 ,  H01L2224/81192 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate.

Abstract translation: 半导体器件包括具有接触焊盘的衬底。 掩模设置在基板上。 铝可润湿的导电浆料印刷在基材的接触垫上。 将半导体管芯设置在铝可润湿的导电膏上。 铝可湿性导电膏被回流以在衬底的接触焊盘上形成互连结构。 接触垫包括铝。 半导体管芯的接触焊盘设置在铝可润湿的导电膏上。 铝可润湿的导电膏被回流以在半导体管芯的接触焊盘和衬底的接触焊盘之间形成互连结构。 互连结构直接形成在基板和半导体管芯的接触焊盘上。 在回流铝可湿性导电膏之前，蚀刻半导体管芯的接触焊盘。 环氧预处理点，以保持半导体管芯和衬底之间的间隔。

公开(公告)号：US20160013148A1

公开(公告)日：2016-01-14

申请号：US14861040

申请日：2015-09-22

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L23/00

CPC classification number: H01L24/19 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/014

Abstract: A semiconductor device has a build-up interconnect structure including a first insulating layer with a first material and a second insulating layer with a second material. A first conductive layer is formed over the first insulating layer, and the second insulating layer is formed over the first conductive layer. An optional third insulating layer has the second material and is formed over the second insulating layer. A fourth insulating layer has the first material and is formed over the third insulating layer. The second, third, and fourth insulating layers are cured sequentially or simultaneously. The first material includes a greater tensile strength, elastic modulus, and CTE than the second material. The build-up interconnect structure is formed over a semiconductor wafer or semiconductor die in a reconstituted panel. Alternatively, the build-up interconnect structure is formed over a carrier and a semiconductor die is mounted over the build-up interconnect structure.

Abstract translation: 半导体器件具有包括具有第一材料的第一绝缘层和具有第二材料的第二绝缘层的堆积互连结构。 第一导电层形成在第一绝缘层上，第二绝缘层形成在第一导电层上。 可选的第三绝缘层具有第二材料并形成在第二绝缘层上。 第四绝缘层具有第一材料并形成在第三绝缘层上。 第二，第三和第四绝缘层依次或同时固化。 第一种材料比第二种材料具有更大的拉伸强度，弹性模量和CTE。 积层互连结构形成在重构面板中的半导体晶片或半导体晶片上。 或者，积累互连结构形成在载体上，半导体管芯安装在积层互连结构上。

公开(公告)号：US20150348861A1

公开(公告)日：2015-12-03

申请号：US14288643

申请日：2014-05-28

Applicant: STATS CHIPPAC, LTD.

Inventor： Lai Yee Chia ,  Duk Ju Na

IPC: H01L23/31 ,  H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L24/97 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/528 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8385 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die disposed over the substrate. A conductive via is formed partially through the substrate. An encapsulant is deposited over the semiconductor die and substrate. An insulating layer is formed over the semiconductor die and encapsulant. The insulating layer includes an organic or inorganic insulating material. An adhesive layer is deposited over the insulating layer. The adhesive layer contacts only the insulating layer. A carrier is bonded to the adhesive layer. The insulating layer provides a single CTE across the entire bonding interface between the adhesive layer and semiconductor die and encapsulant. The constant CTE of the insulating layer reduces stress across the bonding interface. A portion of the substrate is removed by backgrinding to expose the conductive via. An insulating layer is formed over the substrate around the conductive via. An interconnect structure is formed over the conductive via.

Abstract translation: 半导体器件具有设置在衬底上的半导体管芯。 导电通孔部分地形成穿过衬底。 密封剂沉积在半导体管芯和衬底上。 在半导体管芯和密封剂上形成绝缘层。 绝缘层包括有机或无机绝缘材料。 粘合剂层沉积在绝缘层上。 粘合剂层仅接触绝缘层。 载体粘合到粘合剂层上。 绝缘层在粘合剂层和半导体管芯和密封剂之间的整个结合界面上提供单个CTE。 绝缘层的恒定CTE降低了接合界面的应力。 通过背磨去除衬底的一部分以暴露导电通孔。 在导电通孔周围的衬底上形成绝缘层。 在导电通孔上形成互连结构。

公开(公告)号：US20150325553A1

公开(公告)日：2015-11-12

申请号：US14804249

申请日：2015-07-20

Applicant: STATS ChipPAC, Ltd.

Inventor： DongSam Park ,  YongDuk Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/05552 ,  H01L2224/81805 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Abstract translation: 半导体器件具有在衬底的表面上具有第一导电层的衬底和暴露第一导电层的多个空腔。 具有导电TSV的第一半导体管芯被安装到基板的空腔中。 第一绝缘层形成在衬底和第一半导体管芯上并延伸到空腔中以将第一半导体管芯嵌入衬底内。 去除第一绝缘层的一部分以暴露导电TSV。 在导电TSV上形成第二导电层。 去除第一导电层的一部分以形成第一导电层的电通常或电隔离的导电段。 第二绝缘层形成在衬底和第一导电层的导电段上。 第二半导体管芯安装在电连接到第二导电层上的衬底上。

公开(公告)号：US09177930B2

公开(公告)日：2015-11-03

申请号：US13621810

申请日：2012-09-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/136 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014

Abstract: A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

Abstract translation: 倒装芯片半导体封装具有带有多个有源器件的衬底。 接触焊盘形成在与多个有源器件电接触的衬底上。 在基板和中间导电层之间形成钝化层，第二阻挡层和粘附层。 中间导电层与接触垫电接触。 通过在中间导电层上电镀形成铜内核柱。 内芯柱具有矩形，圆柱形，环形或中空圆柱形。 通过电镀焊料材料并回流焊料材料形成焊料凸点，在内芯柱周围形成焊料凸块。 在内芯柱和焊料凸块之间形成第一阻挡层和润湿层。 焊料凸块与中间导电层电接触。

公开(公告)号：US20150311172A1

公开(公告)日：2015-10-29

申请号：US14745056

申请日：2015-06-19

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1411 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17107 ,  H01L2224/27013 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83856 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13109 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的多个复合凸块的半导体管芯。 复合凸块具有可熔部分和不可熔部分，例如形成在导电柱上的导电柱和凸块。 复合凸块也可以是锥形的。 导电迹线形成在具有从平面图平行于导电迹线的边缘的互连位置的衬底上，以增加逃逸路由密度。 互连部位可以具有小于导电迹线宽度的1.2倍的宽度。 复合凸块比互连部位宽。 复合凸块的可熔部分结合到互连部位，使得可熔部分覆盖互连部位的顶表面和侧表面。 围绕半导体管芯和衬底之间的复合凸块沉积密封剂。

公开(公告)号：US09142515B2

公开(公告)日：2015-09-22

申请号：US14087653

申请日：2013-11-22

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  DaeSik Choi ,  Jun Mo Koo

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L23/34 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/34 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/19 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.

Abstract translation: 半导体晶片具有多个第一半导体管芯。 第二半导体管芯安装到第一半导体管芯。 在第一和第二半导体管芯之间形成屏蔽层。 在第一和第二半导体管芯之间形成诸如导电柱，凸起或接合线的电互连。 可以通过第一和第二半导体管芯形成导电TSV。 密封剂沉积在第一和第二半导体管芯和电互连上。 在第二半导体管芯上形成散热器。 可以在第二半导体管芯上形成诸如凸块的互连结构。 去除第一半导体管芯的背面的一部分。 在第一半导体管芯的暴露表面上形成保护层。 保护层覆盖第一半导体管芯的暴露的背面和侧壁。