公开(公告)号：US09922894B1

公开(公告)日：2018-03-20

申请号：US15269629

申请日：2016-09-19

Applicant: FREESCALE SEMICONDUCTOR INC.

Inventor： Lakshminarayan Viswanathan ,  Jaynal A. Molla ,  David Abdo ,  Mali Mahalingam ,  Carl D'Acosta

IPC: H01L23/12 ,  H01L23/66 ,  H01L23/20 ,  H01L23/047 ,  H01L21/48 ,  H01L23/057 ,  H01L23/367 ,  B22F3/10 ,  B22F1/00 ,  B23K35/02 ,  B23K35/30 ,  H01L23/00

CPC classification number: H01L23/20 ,  B22F1/0062 ,  B22F3/10 ,  B22F5/10 ,  B22F7/02 ,  B22F2301/10 ,  B22F2301/255 ,  B22F2302/45 ,  B23K35/025 ,  B23K35/30 ,  H01L21/4817 ,  H01L21/50 ,  H01L23/04 ,  H01L23/047 ,  H01L23/057 ,  H01L23/10 ,  H01L23/3675 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48177 ,  H01L2224/73265 ,  H01L2924/01042 ,  H01L2924/15747 ,  H01L2924/3511

Abstract: Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.

公开(公告)号：US09748185B2

公开(公告)日：2017-08-29

申请号：US15050176

申请日：2016-02-22

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan ,  Jeffrey K. Jones ,  Scott D. Marshall

IPC: H01L27/108 ,  H01L29/94 ,  H01L31/119 ,  H01L23/66 ,  H01L23/047 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/66 ,  H01L23/047 ,  H01L23/49589 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of semiconductor devices (e.g., RF devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit and/or an impedance matching circuit. Embodiments also include method of manufacturing such semiconductor devices.

公开(公告)号：US09111901B2

公开(公告)日：2015-08-18

申请号：US14287142

申请日：2014-05-26

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Jin-Wook Jang ,  Lalgudi M. Mahalingam ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan

IPC: H01L21/302 ,  H01L21/461 ,  H01L23/373 ,  H01L23/057 ,  H01L23/00

CPC classification number: H01L23/373 ,  H01L23/057 ,  H01L23/3731 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/838 ,  H01L2224/83805 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0489 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of methods for forming a semiconductor device that includes a die and a substrate include pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate, and performing a bonding operation to form a die attach layer between the die and the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.

Abstract translation: 用于形成包括管芯和衬底的半导体器件的方法的实施例包括将管芯和衬底压在一起，使得第一金层和一个或多个另外的材料层位于管芯和衬底之间，并且执行接合操作 在管芯和衬底之间形成管芯附着层。 管芯附着层包括金界面层，其包含金和金中的多个第一沉淀物。 每个第一沉淀物包括镍，钴，钯，金和硅的组合。

公开(公告)号：US09986646B2

公开(公告)日：2018-05-29

申请号：US14549934

申请日：2014-11-21

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Lakshminarayan Viswanathan ,  Audel A. Sanchez ,  Fernando A. Santos ,  Jerry L. White

IPC: H05K1/18 ,  H05K3/28 ,  H05K1/16 ,  H05K7/00 ,  H05K9/00 ,  H01L21/56 ,  H01L33/52 ,  H01L31/0203 ,  H01L23/28 ,  H01L23/22 ,  H01L31/048 ,  H05K3/34

CPC classification number: H05K3/284 ,  H01L21/56 ,  H01L23/22 ,  H01L23/28 ,  H01L31/0203 ,  H01L31/048 ,  H01L33/52 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/73227 ,  H01L2224/73267 ,  H01L2224/92164 ,  H01L2224/92244 ,  H05K1/185 ,  H05K3/3421 ,  H05K9/0052 ,  H05K9/0081 ,  H05K2201/10166 ,  H05K2201/10371 ,  H05K2201/10977 ,  H05K2203/1316 ,  H05K2203/1327

Abstract: An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.

公开(公告)号：US09984951B2

公开(公告)日：2018-05-29

申请号：US15223307

申请日：2016-07-29

Applicant: FREESCALE SEMICONDUCTOR INC.

Inventor： Lakshminarayan Viswanathan

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/00 ,  B22F7/08

CPC classification number: H01L23/3735 ,  B22F5/006 ,  B22F7/04 ,  B22F7/08 ,  B22F2007/042 ,  B22F2999/00 ,  B32B15/01 ,  H01L21/4882 ,  H01L23/057 ,  H01L23/3736 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48175 ,  H01L2224/73265 ,  B22F1/0059 ,  B22F3/1121

Abstract: Methods for producing multilayer heat sinks utilizing low temperature sintering processes are provided. In one embodiment, the method includes forming a metal particle-containing precursor layer over a first principal surface of a first metal layer. The first metal layer and the metal particle-containing layer are then arranged in a stacked relationship with a second metal layer such that the precursor layer is disposed between the first and second metal layers. A low temperature sintering process is then carried-out at a maximum process temperature less than a melt point of the metal particles to transform the precursor layer into a sintered bond layer joining the first and second metal layers in a sintered multilayer heat sink. In embodiments wherein the sintered multilayer heat sink is contained within a heat sink panel, singulation may be carried-out to separate the sintered multilayer heat sink from the other heat sinks within the panel.

公开(公告)号：US09837328B2

公开(公告)日：2017-12-05

申请号：US15070308

申请日：2016-03-15

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/047 ,  H01L23/00 ,  H01L23/057 ,  H01L23/31 ,  H01L23/14 ,  H01L23/367 ,  H01L21/50 ,  H01L23/492 ,  H01L23/498 ,  H01L25/065 ,  H01L21/288 ,  H01L21/48

CPC classification number: H01L23/047 ,  H01L21/288 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/50 ,  H01L23/057 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/4924 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0655 ,  H01L2224/2731 ,  H01L2224/29139 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0461 ,  H01L2924/0469 ,  H01L2924/1421 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/16152 ,  H01L2924/16598 ,  H01L2924/171 ,  H01L2924/181 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

公开(公告)号：US20160365323A1

公开(公告)日：2016-12-15

申请号：US15247393

申请日：2016-08-25

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan ,  Jaynal A. Molla

IPC: H01L23/00 ,  H01L29/16 ,  H01L21/48 ,  H01L23/48 ,  H01L23/495 ,  H01L21/78 ,  H01L29/20 ,  H01L23/66

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/741 ,  H01L24/743 ,  H01L24/92 ,  H01L24/94 ,  H01L29/16 ,  H01L29/2003 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/03436 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03505 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/05844 ,  H01L2224/05847 ,  H01L2224/05855 ,  H01L2224/05864 ,  H01L2224/05887 ,  H01L2224/0589 ,  H01L2224/05893 ,  H01L2224/27002 ,  H01L2224/2731 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/27438 ,  H01L2224/27505 ,  H01L2224/29006 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29015 ,  H01L2224/29017 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29084 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29117 ,  H01L2224/29118 ,  H01L2224/2912 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2918 ,  H01L2224/29184 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/296 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/741 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/1016 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1421 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/3512 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/01015 ,  H01L2924/01048 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01028 ,  H01L2924/01027 ,  H01L2924/01026 ,  H01L2224/03 ,  H01L2224/05099 ,  H01L2924/01006 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2224/83 ,  H01L2924/0781 ,  H01L2924/00 ,  H01L2224/034 ,  H01L2221/68368 ,  H01L2224/274

Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

Abstract translation: 电子器件包括具有下表面的半导体管芯，位于半导体管芯的下表面下方的烧结金属层，位于烧结金属层下面的导电层，以及导电层下面的导电基底。

公开(公告)号：US20140084432A1

公开(公告)日：2014-03-27

申请号：US13624232

申请日：2012-09-21

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Fernando A. Santos ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan

IPC: H01L23/495 ,  H01L21/60 ,  H01L23/48

CPC classification number: H01L25/0655 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49579 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29116 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/85801 ,  H01L2224/8584 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/181 ,  H01L2924/20106 ,  H01L2924/20755 ,  H01L2924/2076 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13099

Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A first electrical interconnect couples the die and the leadframe. A housing covers portions of the leadframe, die carrier, die and first electrical interconnect.

Abstract translation: 封装的半导体器件可以包括安装到引线框的引线框架和管芯载体。 模具载体由导电和导热材料形成。 模具安装到模具载体的表面，模头附着材料具有超过240℃的熔点。第一电互连使模具和引线框架相连。 壳体覆盖引线框架，管芯载体，管芯和第一电互连部分。

公开(公告)号：US09799580B2

公开(公告)日：2017-10-24

申请号：US15079276

申请日：2016-03-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Li Li ,  Jaynal A. Molla ,  Lakshminarayan Viswanathan

IPC: H01L23/34 ,  H01L23/047 ,  H01L21/56 ,  H01L21/52 ,  H01L21/50 ,  H01L23/373 ,  H01L23/00 ,  H01L21/603 ,  H01L21/60

CPC classification number: H01L23/047 ,  H01L21/50 ,  H01L21/52 ,  H01L21/566 ,  H01L23/3157 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/4334 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2021/60277 ,  H01L2021/603 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29393 ,  H01L2224/29399 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/8384 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/16195 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/00

Abstract: A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.

公开(公告)号：US09614046B2

公开(公告)日：2017-04-04

申请号：US15173487

申请日：2016-06-03

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan ,  Bruce M. Green ,  Darrell G. Hill ,  L. M. Mahalingam

IPC: H01L31/102 ,  H01L29/417 ,  H01L23/367 ,  H01L21/762 ,  H01L21/3205 ,  H01L21/04 ,  H01L21/28 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L23/48 ,  H01L23/373

CPC classification number: H01L23/373 ,  H01L21/042 ,  H01L21/0475 ,  H01L21/28 ,  H01L21/32051 ,  H01L21/762 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/04026 ,  H01L2224/29026 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.