公开(公告)号：US08836130B2

公开(公告)日：2014-09-16

申请号：US13333569

申请日：2011-12-21

申请人： Masafumi Kuramoto ,  Satoru Ogawa ,  Teppei Kunimune

发明人： Masafumi Kuramoto ,  Satoru Ogawa ,  Teppei Kunimune

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/18 ,  H01L23/00 ,  H01L33/62

CPC分类号： H01L21/187 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/05639 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29 ,  H01L2224/2908 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/83411 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/85205 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01063 ,  H01L2924/01064 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2924/0541 ,  H01L2924/00014 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/83205

摘要： An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. In the semiconductor device, silver arranged on a semiconductor element and silver arranged on a base are bonded. No void is present or a small void, if any, is present at an interface between the semiconductor element and the silver arranged on the semiconductor element, no void is present or a small void, if any, is present at an interface between the base and the silver arranged on the base, and one or more silver abnormal growth grains and one or more voids are present in a bonded interface between the silver arranged on the semiconductor element and the silver arranged on the base.

摘要翻译： 本发明的目的是提供一种用于制造具有低电阻的导电构件的方法，并且使用不含粘合剂的低成本稳定的导电材料组合物获得导电构件。 在半导体装置中，配置在半导体元件上的银和布置在基底上的银结合。 不存在空隙，或半导体元件与布置在半导体元件上的银之间的界面存在小空隙（如果有的话），则不存在空隙，或者存在小空隙（如果有的话）存在于基底 并且布置在基底上的银和在布置在半导体元件上的银和布置在基底上的银之间的结合界面中存在一个或多个银异常生长晶粒和一个或多个空隙。

公开(公告)号：US08836085B2

公开(公告)日：2014-09-16

申请号：US14018210

申请日：2013-09-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ku-Feng Yang ,  Yung-Chi Lin ,  Hung-Pin Chang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13025 ,  H01L2924/00013 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other.

摘要翻译： 一种器件包括具有第一表面的衬底和与第一表面相对的第二表面。 贯穿基板通孔（TSV）从基板的第一表面延伸到第二表面。 电介质层设置在衬底上。 金属焊盘设置在电介质层中并物理接触TSV，其中金属焊盘和TSV由相同的材料形成，并且其中由不同于相同材料的材料形成的层不在其间并且使TSV和 金属垫彼此分开。

公开(公告)号：US20140252613A1

公开(公告)日：2014-09-11

申请号：US14279852

申请日：2014-05-16

申请人： Yoshinori IWAMOTO ,  Kouji SATO ,  Yutaka NAKAJIMA ,  Ken HAYAKAWA

发明人： Yoshinori IWAMOTO ,  Kouji SATO ,  Yutaka NAKAJIMA ,  Ken HAYAKAWA

IPC分类号： H01L25/065 ,  H01L23/00

CPC分类号： H01L24/14 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/2732 ,  H01L2224/29099 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/92147 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/85399 ,  H01L2224/05599

摘要： The present invention reduces the occurrence of fracture in external terminal connecting sections and improves the reliability of secondary packaging of a semiconductor device. Specifically, the present invention provides a semiconductor device including a wiring board, a semiconductor chip mounted on one surface of the wiring board via a bonding member, and external electrodes formed on the other surface of the wiring board and electrically connected to the semiconductor chip. In the semiconductor device, a peripheral end of the bonding member is arranged in a position where the peripheral end does not overlap the external electrodes.

摘要翻译： 本发明可减少外部端子连接部的断裂的发生，提高半导体器件的二次封装的可靠性。 具体地说，本发明提供一种半导体器件，其包括布线板，通过接合部件安装在布线板的一个表面上的半导体芯片，以及形成在布线板的另一个表面上并与半导体芯片电连接的外部电极。 在半导体器件中，接合部件的外周端部配置在外周端不与外部电极重叠的位置。

公开(公告)号：US20140252570A1

公开(公告)日：2014-09-11

申请号：US14285079

申请日：2014-05-22

申请人： GILLES MONTORIOL ,  THIERRY DELAUNAY ,  FREDERIC TILHAC

发明人： GILLES MONTORIOL ,  THIERRY DELAUNAY ,  FREDERIC TILHAC

IPC分类号： H01L23/495

CPC分类号： H01L23/49531 ,  H01L23/49575 ,  H01L23/64 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2223/6644 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099

摘要： A lead-frame circuit package comprises a die and a substrate located thereon to route radio frequency signals to/from the die. The package preferably comprises an exposed pad on the die to receive a power amplifier device wherein the substrate is used to provide high-Q elements such as RF chokes on signal paths to/from the power amplifier device.In this manner, the design benefits from the power capabilities and improved grounding of a lead-frame conductor, whilst also achieving the routeing capabilities and small scale advantages provided by a multi-layer printed circuit substrate.

摘要翻译： 引线框电路封装包括管芯和位于其上的衬底以将射频信号传送到管芯或从管芯移出。 封装优选地包括裸片上的裸露焊盘以接收功率放大器器件，其中衬底用于在/从功率放大器器件的信号路径上提供高Q元件，例如RF扼流圈。 以这种方式，该设计受益于引线框导体的功率能力和改进的接地，同时还实现了由多层印刷电路基板提供的路由能力和小规模优点。

公开(公告)号：US20140231966A1

公开(公告)日：2014-08-21

申请号：US14260205

申请日：2014-04-23

申请人： XINTEC INC.

发明人： Bai-Yao LOU ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Tzu-Hsiang HUNG

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/73153 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括具有第一表面和第二表面的基板; 位于所述第一表面上的导电垫结构; 位于所述基板的所述第一表面上的电介质层和所述导电焊盘结构，其中所述电介质层具有暴露所述导电焊盘结构的一部分的开口; 以及位于电介质层上并填充到开口中的盖层。

公开(公告)号：US20140225274A1

公开(公告)日：2014-08-14

申请号：US14130362

申请日：2012-06-26

申请人： Michael Guyenot ,  Michael Guenther ,  Thomas Herboth

发明人： Michael Guyenot ,  Michael Guenther ,  Thomas Herboth

IPC分类号： H01L23/00

CPC分类号： H01L24/64 ,  H01L23/3735 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/70 ,  H01L24/83 ,  H01L2224/2732 ,  H01L2224/27418 ,  H01L2224/27848 ,  H01L2224/29 ,  H01L2224/29007 ,  H01L2224/29012 ,  H01L2224/29015 ,  H01L2224/29023 ,  H01L2224/29036 ,  H01L2224/29139 ,  H01L2224/29298 ,  H01L2224/3003 ,  H01L2224/30051 ,  H01L2224/3012 ,  H01L2224/30142 ,  H01L2224/3016 ,  H01L2224/30181 ,  H01L2224/32014 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/83048 ,  H01L2224/83203 ,  H01L2224/8384 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/07811 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1517 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for producing a sinter layer connection between a substrate and a chip resulting in an electric and thermal connection therebetween and in reduced mechanical tensions within the chip. The method produces a sinter layer by applying a multitude of sinter elements of a base material forming the sinter layer in structured manner on a contact area of a main surface of a substrate; placing a chip to be joined to the substrate on the sinter elements; and heating and compressing the sinter elements to produce a structured sinter layer connecting the substrate and chip and extending within the contact area, the surface coverage density of the sinter elements on the substrate in a center region of the contact area being greater than the surface coverage density of the sinter elements in an edge region of the contact area, and at least one through channel, extending laterally as to the substrate's main surface being provided towards the contact area's edge. A large-area sinter element is situated in the contact area's center region, and circular sinter elements is situated in a contact area edge region. The sinter elements may also have notches. Also described is a related device.

摘要翻译： 一种用于在基板和芯片之间产生烧结层连接的方法，其导致其间的电和热连接以及芯片内的减小的机械张力。 该方法通过将形成烧结层的基体材料的大量烧结元件以结构的方式施加到衬底的主表面的接触区域上来产生烧结层; 将要接合到所述基板上的芯片放置在所述烧结元件上; 并且对所述烧结元件进行加热和压缩以产生连接所述衬底和所述芯片并且在所述接触区域内延伸的结构化烧结层，所述接触区域的中心区域中的所述衬底上的所述烧结元件的表面覆盖密度大于所述表面覆盖度 所述接触区域的边缘区域中的所述烧结元件的密度以及至少一个穿过所述衬底主表面横向延伸的贯穿通道朝向所述接触区域的边缘设置。 大面积烧结体位于接触区域的中心区域，圆形烧结体位于接触区边缘区域。 烧结体也可以具有凹口。 还描述了相关设备。

公开(公告)号：US08803338B2

公开(公告)日：2014-08-12

申请号：US14057045

申请日：2013-10-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Fu Tsai ,  Yian-Liang Kuo ,  Chih-Horng Chang

IPC分类号： H01L23/02

CPC分类号： H01L23/49811 ,  H01L21/76885 ,  H01L21/76886 ,  H01L23/535 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03848 ,  H01L2224/03901 ,  H01L2224/03903 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/013 ,  H01L2924/01046 ,  H01L2924/01039 ,  H01L2924/01016 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01028 ,  H01L2224/034 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device comprises a semiconductor substrate, an under-bump metallization (UBM) structure overlying the semiconductor substrate, and a solder bump overlying and electrically connected to the UBM structure. The UBM structure comprises a copper-containing metallization layer, a nickel-containing metallization layer, and a first intermetallic compound (IMC) layer between the copper-containing metallization layer and the nickel-containing metallization layer. The first IMC layer is in direct contact with the copper-containing metallization layer and the nickel-containing metallization layer.

摘要翻译： 半导体器件包括半导体衬底，覆盖半导体衬底的凸起下金属化（UBM）结构以及覆盖并电连接到UBM结构的焊料凸块。 UBM结构包括含铜金属化层，含镍金属化层和位于含铜金属化层和含镍金属化层之间的第一金属间化合物（IMC）层。 第一IMC层与含铜金属化层和含镍金属化层直接接触。

公开(公告)号：US08796787B2

公开(公告)日：2014-08-05

申请号：US14040483

申请日：2013-09-27

申请人： Renesas Electronics Corporation

发明人： Tomohiro Tamaki ,  Yoshito Nakazawa

IPC分类号： H01L27/088

CPC分类号： H01L29/7811 ,  H01L23/3107 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7816 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/29099

摘要： In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

摘要翻译： 在诸如在有源单元区域和芯片外围区域中的每一个中具有超结结构的功率MOSFET的半导体功率器件中，第二导电类型的表面区域的外端与第二导电性的主结 类型在第一导电类型的漂移区的表面中并且具有低于主结的浓度的漂移区的表面位于主结的外端和超结结构的外端之间的中间区域 芯片外围区域。

公开(公告)号：US20140203444A1

公开(公告)日：2014-07-24

申请号：US14225923

申请日：2014-03-26

申请人： FUJITSU LIMITED

发明人： KOZO SHIMIZU ,  KEISHIRO OKAMOTO ,  NOBUHIRO IMAIZUMI ,  TADAHIRO IMADA ,  KEIJI WATANABE

IPC分类号： H01L23/48

CPC分类号： H01L23/48 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/26175 ,  H01L2224/2745 ,  H01L2224/2746 ,  H01L2224/29019 ,  H01L2224/29036 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/325 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48644 ,  H01L2224/48744 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/13064 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83439 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0132 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.

摘要翻译： 半导体器件的制造包括在支撑板的半导体芯片安装区域和半导体芯片的后表面中的一个上形成具有第一金属的层和具有第二金属的层; 在第一金属层和第二金属层之间形成与第一金属层和第二金属层之间的一个区域对应的区域的另一层 的半导体芯片安装区域和半导体芯片的背面; 以及在将所述半导体芯片定位在所述半导体芯片安装区域中之后，形成与所述第一金属和所述第二金属合金的层，以将半导体芯片与半导体芯片安装区域接合。

公开(公告)号：US08781435B2

公开(公告)日：2014-07-15

申请号：US12703585

申请日：2010-02-10

申请人： Peerapol Tinnakornsrisuphap ,  Jen Mei Chen

发明人： Peerapol Tinnakornsrisuphap ,  Jen Mei Chen

IPC分类号： H04M11/00

CPC分类号： H04W36/0016 ,  H01L2924/00013 ,  H04L29/12066 ,  H04L29/1282 ,  H04L61/1511 ,  H04L61/6013 ,  H01L2224/29099

摘要： Systems and methods for identifying an address of a femto node during handoff of an access terminal from a femto node to a macro node. In one embodiment, the femto node assigns a unique identifier to the access terminal. The access terminal passes the unique identifier to the macro node. The macro node partitions the unique identifier to determine the address of the femto node. In another embodiment, the femto node registers its address with a domain name system. The macro node queries the domain name system to obtain the address of the femto node. In another embodiment, the macro node sends the unique identifier to a proxy. The proxy partitions the unique identifier to determine the address of the femto node.