公开(公告)号：US08884418B2

公开(公告)日：2014-11-11

申请号：US13606451

申请日：2012-09-07

Applicant: Zigmund R. Camacho ,  Frederick R. Dahilig ,  Lionel Chien Hui Tay

Inventor： Zigmund R. Camacho ,  Frederick R. Dahilig ,  Lionel Chien Hui Tay

IPC: H01L23/24 ,  H01L23/28 ,  H01L23/48 ,  H01L25/11 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/495

CPC classification number: H01L23/49548 ,  H01L21/4832 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49541 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83411 ,  H01L2224/83424 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/85001 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.

Abstract translation: PiP半导体器件具有内部已知的良好半导体封装。 在半导体封装中，在临时载体中形成第一通孔。 第一导电层形成在载体上并进入第一通孔中。 第一通孔中的第一导电层形成导电凸块。 第一半导体管芯安装到第一导电层。 第一密封剂沉积在第一模具和载体上。 半导体封装被安装到基板上。 第二半导体管芯安装到与第一管芯相对的第一导电层。 第二密封剂沉积在第二管芯和半导体封装上。 在第二密封剂中形成第二通孔以暴露导电凸块。 第二导电层形成在第二密封剂上并进入第二通孔中。 第二导电层电连接到第二管芯。

公开(公告)号：US08878359B2

公开(公告)日：2014-11-04

申请号：US13766493

申请日：2013-02-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng ,  Xusheng Bao

IPC: H01L23/13 ,  H01L23/14 ,  H01L23/485 ,  H01L23/488 ,  H01L21/56 ,  H01L23/29 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/28 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14135 ,  H01L2224/221 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

Abstract translation: 多个半导体管芯安装到临时载体上。 密封剂沉积在半导体管芯和载体上。 密封剂的一部分被指定为模具之间的锯道，并且密封剂的一部分被指定为围绕密封剂的周边的基底边缘。 载体被移除。 在模具，锯条和基板边缘上形成第一绝缘层。 在第一绝缘层上形成第一导电层。 在第一导电层和第一绝缘层上形成第二绝缘层。 通过第一绝缘层和锯条将密封剂分离，以分离半导体管芯。 可以在锯条的相对侧的第一绝缘层中形成通道或网状图案，或者第一绝缘层覆盖整个锯条和半导体管芯周围的成型区域。

公开(公告)号：US08877101B2

公开(公告)日：2014-11-04

申请号：US13223293

申请日：2011-08-31

Applicant: Mark D. Lowenthal ,  William Johnstone Ray ,  Neil O. Shotton ,  Richard A. Blanchard ,  Mark Allan Lewandowski ,  Brad Oraw ,  Jeffrey Baldridge ,  Eric Anthony Perozziello

Inventor： Mark D. Lowenthal ,  William Johnstone Ray ,  Neil O. Shotton ,  Richard A. Blanchard ,  Mark Allan Lewandowski ,  Brad Oraw ,  Jeffrey Baldridge ,  Eric Anthony Perozziello

IPC: H01L33/20 ,  H01L23/00 ,  H01L51/52 ,  H01L51/56 ,  H01L25/04 ,  H01L27/32 ,  H01L33/38 ,  H01L21/683

CPC classification number: H01L27/3281 ,  H01L21/6836 ,  H01L24/24 ,  H01L24/95 ,  H01L25/048 ,  H01L27/142 ,  H01L27/15 ,  H01L27/301 ,  H01L27/32 ,  H01L31/03044 ,  H01L31/035281 ,  H01L31/0475 ,  H01L31/068 ,  H01L31/1876 ,  H01L33/005 ,  H01L33/20 ,  H01L33/38 ,  H01L33/382 ,  H01L51/42 ,  H01L51/52 ,  H01L51/5203 ,  H01L51/56 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/95101 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13033 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  Y02E10/544 ,  Y02E10/547 ,  Y02P70/521 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary method of fabricating an electronic device comprises: depositing one or more first conductors; and depositing a plurality of diodes suspended in a mixture of a first solvent and a viscosity modifier. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns.

Abstract translation: 二极管的液体或凝胶悬浮液的示例性可印刷组合物包括多个二极管，第一溶剂和/或粘度调节剂。 制造电子设备的示例性方法包括：沉积一个或多个第一导体; 以及沉积悬浮在第一溶剂和粘度调节剂的混合物中的多个二极管。 各种示例性二极管的高度为约10至50微米和约5至25微米之间的横向尺寸。 其它实施方案还可以包括多个基本上化学惰性的颗粒，其尺寸范围在约10至约50微米之间。

公开(公告)号：US08872335B2

公开(公告)日：2014-10-28

申请号：US11781282

申请日：2007-07-23

Applicant: Holger Huebner ,  Martin Franosch

Inventor： Holger Huebner ,  Martin Franosch

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H05K3/30 ,  H01L23/00 ,  H01L23/498 ,  H05K3/28

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/8383 ,  H01L2224/83862 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/284 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/0783 ,  H05K2203/306 ,  Y02P70/613 ,  H01L2924/00

Abstract: It is proposed a method of manufacturing an electronic system wherein a first substrate comprising first connection elements on a first surface of the first substrate is provided; a second substrate comprising second connection elements on a first surface of the second substrate is provided; a polymer layer is applied to at least one of the two first surfaces; the first connection elements are attached to the second connection elements; and the polymer layer is caused to swell during or after the attachment.

Abstract translation: 提出了一种制造电子系统的方法，其中提供包括在第一基板的第一表面上的第一连接元件的第一基板; 提供包括在第二基板的第一表面上的第二连接元件的第二基板; 将聚合物层施加到两个第一表面中的至少一个上; 第一连接元件附接到第二连接元件; 并且在附着期间或之后使聚合物层膨胀。

公开(公告)号：US20140312539A1

公开(公告)日：2014-10-23

申请号：US14320765

申请日：2014-07-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshiko OKADA ,  Osamu CHIKAGAWA ,  Hidekiyo TAKAOKA ,  Shodo TAKEI

IPC: H05K3/46

CPC classification number: H05K3/4629 ,  H01G2/02 ,  H01G4/005 ,  H01G4/30 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/01004 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/186 ,  H05K3/4611 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49155

Abstract: A ceramic multilayer substrate incorporating a chip-type ceramic component, in which, even if the chip-type ceramic component is mounted on the surface of the ceramic multilayer substrate, bonding strength between the chip-type ceramic component and an internal conductor or a surface electrode of the ceramic multilayer substrate is greatly improved and increased. The ceramic multilayer substrate includes a ceramic laminate in which a plurality of ceramic layers are stacked, an internal conductor disposed in the ceramic laminate, a surface electrode disposed on the upper surface of the ceramic laminate, and a chip-type ceramic component bonded to the internal conductor or the surface electrode through an external electrode. The internal conductor or the surface electrode is bonded to the external electrode through a connecting electrode, and the connecting electrode forms a solid solution with any of the internal conductor, the surface electrode, and the external electrode.

Abstract translation: 另外，在芯片型陶瓷部件的陶瓷多层基板中，即使在陶瓷多层基板的表面上安装有芯片型陶瓷部件，也可以将芯片型陶瓷部件与内部导体或表面 陶瓷多层基板的电极大大改善和增加。 陶瓷多层基板包括层叠有多个陶瓷层的陶瓷层叠体，设置在陶瓷层叠体中的内部导体，设置在陶瓷层叠体的上表面的表面电极以及与该陶瓷层叠体接合的芯片型陶瓷构件 内部导体或表面电极通过外部电极。 内部导体或表面电极通过连接电极接合到外部电极，连接电极与内部导体，表面电极和外部电极中的任一个形成固溶体。

公开(公告)号：US08866236B2

公开(公告)日：2014-10-21

申请号：US12769993

申请日：2010-04-29

Applicant: Chi-Hsin Chiu ,  Chih-Ming Huang ,  Chang-Yueh Chan ,  Hsin-Yi Liao ,  Chun-Chi Ke

Inventor： Chi-Hsin Chiu ,  Chih-Ming Huang ,  Chang-Yueh Chan ,  Hsin-Yi Liao ,  Chun-Chi Ke

IPC: H01L29/84 ,  H01L23/31 ,  H01L21/56 ,  B81B7/00 ,  H01L23/552 ,  H01L23/00

CPC classification number: B81B7/0064 ,  B81B7/007 ,  B81B2207/095 ,  H01L21/56 ,  H01L23/315 ,  H01L23/552 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.

Abstract translation: 提供具有至少MEMS元件的封装结构，其包括具有电连接焊盘和MEMS元件的芯片; 设置在所述芯片上以覆盖所述MEMS元件并且具有设置在其上的金属层的盖; 电连接到电连接焊盘的第一子接合线; 电连接到金属层的第二子接合线; 设置在所述芯片上的密封剂，其中所述第一和第二子接合线的顶端从所述密封剂露出; 以及设置在密封剂上并电连接到第一子接合线的金属迹线。 封装结构有利地具有减小的尺寸，相对低的成本，不同的凸起位置和增强的EMI屏蔽效果。

公开(公告)号：US08853868B2

公开(公告)日：2014-10-07

申请号：US14059548

申请日：2013-10-22

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt ,  Marc A. Sulfridge

IPC: H01L23/544 ,  G03F9/00 ,  H01L27/146 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/544 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14618 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/09701 ,  Y10T428/24322 ,  H01L2924/014

Abstract: A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed.

Abstract translation: 公开了一种制造半分辨率对准标记的半导体结构的方法。 该方法包括在衬底上形成电介质材料并且形成部分地延伸到电介质材料中的至少一个次分辨率对准标记。 在电介质材料中形成至少一个开口。 还公开了包括子分辨率对准标记的半导体结构。

公开(公告)号：US08853799B2

公开(公告)日：2014-10-07

申请号：US14041745

申请日：2013-09-30

Applicant: Analog Devices, Inc.

Inventor： Alan J. O'Donnell ,  Santiago Iriarte ,  Mark J. Murphy ,  Colin G. Lyden ,  Gary Casey ,  Eoin Edward English

IPC: H01L27/15 ,  H01L25/16 ,  H01L49/02 ,  H01L23/48 ,  G01N27/26 ,  H01L21/82 ,  H01F17/00 ,  B81B7/00 ,  H02S10/10 ,  H01L31/053 ,  G01N27/414 ,  H01L27/14 ,  H01L31/0392 ,  H01L27/06 ,  H01L23/473 ,  H01L23/367 ,  H01L23/38

CPC classification number: G01N27/226 ,  B81B7/00 ,  B81B7/007 ,  B81B2201/0214 ,  G01N27/26 ,  G01N27/4148 ,  H01F17/00 ,  H01F17/04 ,  H01L21/82 ,  H01L23/3677 ,  H01L23/38 ,  H01L23/473 ,  H01L23/481 ,  H01L23/58 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L24/94 ,  H01L25/16 ,  H01L25/167 ,  H01L27/0694 ,  H01L27/14 ,  H01L27/15 ,  H01L28/00 ,  H01L28/10 ,  H01L28/20 ,  H01L28/60 ,  H01L28/82 ,  H01L28/86 ,  H01L28/90 ,  H01L31/0392 ,  H01L31/0525 ,  H01L31/0547 ,  H01L31/056 ,  H01L31/06 ,  H01L35/00 ,  H01L35/28 ,  H01L35/30 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48265 ,  H01L2225/06531 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H02S10/10 ,  H02S40/38 ,  Y02E10/50 ,  Y02E10/52 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05552 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

公开(公告)号：US20140284788A9

公开(公告)日：2014-09-25

申请号：US13606451

申请日：2012-09-07

Applicant: Zigmund R. Camacho ,  Frederick R. Dahilig ,  Lionel Chien Hui Tay

Inventor： Zigmund R. Camacho ,  Frederick R. Dahilig ,  Lionel Chien Hui Tay

IPC: H01L23/485

CPC classification number: H01L23/49548 ,  H01L21/4832 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49541 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83411 ,  H01L2224/83424 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/85001 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.

Abstract translation: PiP半导体器件具有内部已知的良好半导体封装。 在半导体封装中，在临时载体中形成第一通孔。 第一导电层形成在载体上并进入第一通孔中。 第一通孔中的第一导电层形成导电凸块。 第一半导体管芯安装到第一导电层。 第一密封剂沉积在第一模具和载体上。 半导体封装被安装到基板上。 第二半导体管芯安装到与第一管芯相对的第一导电层。 第二密封剂沉积在第二管芯和半导体封装上。 在第二密封剂中形成第二通孔以暴露导电凸块。 第二导电层形成在第二密封剂上并进入第二通孔中。 第二导电层电连接到第二管芯。

公开(公告)号：US08841762B2

公开(公告)日：2014-09-23

申请号：US13440337

申请日：2012-04-05

Applicant: Yugo Koyama

Inventor： Yugo Koyama

IPC: H01L23/48 ,  H01L21/00 ,  G01C19/5783 ,  H01L23/31 ,  G01C19/5621 ,  H01L23/055

CPC classification number: G01C19/5783 ,  B81B7/0074 ,  B81B2201/025 ,  G01C19/5621 ,  H01L23/055 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A sensor module includes a support member having a first flat surface, a second flat surface orthogonally connected to the first flat surface, a third flat surface orthogonally connected to the first flat surface and the second flat surface, and a fourth flat surface opposed to the first flat surface as an attachment surface to an external member, the first flat surface having a support surface depressed from the first flat surface, IC chips having connection terminals on active surface sides with inactive surface sides along the active surfaces respectively attached to the respective surfaces of the support member, and vibration gyro elements having connection electrodes, and the vibration gyro elements are provided on the active surface sides of the IC chips and the connection electrodes are attached to the connection terminals of the IC chips so that principal surfaces are respectively along the respective surfaces of the support member.

Abstract translation: 传感器模块包括具有第一平坦表面的支撑构件，与第一平坦表面正交连接的第二平坦表面，与第一平坦表面和第二平坦表面正交连接的第三平坦表面和与第一平坦表面相对的第四平坦表面 所述第一平面具有从所述第一平面凹下的支撑面，所述第一平面具有从所述第一平面凹下的支撑面，所述IC芯片具有在所述有源面侧的连接端子，所述IC芯片沿着所述有源面分别具有不平坦的表面侧， 和具有连接电极的振动陀螺元件，并且振动陀螺元件设置在IC芯片的有源面侧，并且连接电极附接到IC芯片的连接端子，使得主表面分别沿着 支撑构件的各个表面。