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    CARRIER-LESS SILICON INTERPOSER
    186.
    发明申请
    CARRIER-LESS SILICON INTERPOSER 有权
    无载体硅介质

    公开(公告)号：US20140240938A1

    公开(公告)日：2014-08-28

    申请号：US13776035

    申请日：2013-02-25

    Applicant: INVENSAS CORPORATION

    Inventor： Michael Newman ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Pezhman Monadgemi ,  Terrence Caskey

    IPC: H05K1/11 ,  H05K3/40

    CPC classification number: H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/16225 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/4038 ,  Y10T29/49117

    Abstract: An interposer can have conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component can include a first element having a thermal expansion coefficient less than 10 ppm/° C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. Conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements.

    Abstract translation: 插入件可以在第一侧具有导电元件，并且在与其相对的第二侧具有端子，用于分别与微电子元件和第二元件连接。 该组件可以包括具有小于10ppm /℃的热膨胀系数的第一元件和绝缘的第二元件，其中多个开口从第二侧延伸穿过第二元件朝向第一元件。 延伸穿过第二元件中的开口并通过第一元件的导电结构将端子与导电元件电连接。

    METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING
    187.
    发明申请
    METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING 有权
    无载波干扰处理的方法和结构

    公开(公告)号：US20140179099A1

    公开(公告)日：2014-06-26

    申请号：US13724223

    申请日：2012-12-21

    Applicant: INVENSAS CORPORATION

    Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Michael Newman ,  Charles G. Woychik ,  Terrence Caskey

    IPC: H01L21/768

    CPC classification number: H01L21/76898 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/481 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

    Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.

    Abstract translation: 本文公开了形成微电子组件的方法以及所得到的结构和装置。 在一个实施例中，形成微电子组件的方法包括去除在衬底的表面的部分处暴露的材料，以形成经处理的衬底，该衬底具有多个由处理衬底的整体支撑部分分隔开的薄化部分，该部分的厚度大于厚度 减薄部分中的至少一些薄化部分包括在薄壁部分的厚度方向上延伸并在表面露出的多个导电互连件; 以及去除衬底的支撑部分以将衬底切割成多个单独的薄化部分，至少一些单独的变薄部分，包括互连。

    Z-CONNECTION USING ELECTROLESS PLATING
    188.
    发明申请
    Z-CONNECTION USING ELECTROLESS PLATING 有权
    使用电镀镀层的Z型连接

    公开(公告)号：US20140131875A1

    公开(公告)日：2014-05-15

    申请号：US13675445

    申请日：2012-11-13

    Applicant: INVENSAS CORPORATION

    Inventor： Belgacem Haba ,  Cyprian Emeka Uzoh

    IPC: H01L23/532 ,  H01L21/50

    CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/53209 ,  H01L24/83 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/808 ,  H01L2224/8385 ,  H01L2224/8389 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2924/15311 ,  H01L2924/2064

    Abstract: In one embodiment, an assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor.

    Abstract translation: 在一个实施例中，组件包括具有衬底导体的衬底和在第一表面处的触点和在第二表面处的端子，用于将组件与组件外部的部件电连接，衬底导体或触点中的至少一个 与终端电连接; 第一元件，其具有面向基板的第一表面的第一表面，并且在第一表面具有第一导体，在第二表面具有第二导体，互连结构，延伸穿过第一元件，电连接第一和第二导体; 粘接所述第一元件和所述基板的所述第一表面的粘合剂层，所述第一导体和所述基板导体的至少一部分设置在所述粘合剂层的边缘之外; 以及在第一导体和衬底导体之间延伸的连续化学镀金属区域。

    DIRECT-BONDED LED ARRAYS AND APPLICATIONS
    189.
    发明申请
    DIRECT-BONDED LED ARRAYS AND APPLICATIONS 有权

    公开(公告)号：US20210288037A1

    公开(公告)日：2021-09-16

    申请号：US17327169

    申请日：2021-05-21

    Applicant: Invensas Corporation

    Inventor： Min Tao ,  Liang Wang ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

    IPC: H01L25/16 ,  H01L33/00 ,  H01L25/10 ,  H01L27/12 ,  H01L27/15 ,  H01L25/18 ,  H01L21/321 ,  H01L21/02 ,  H01L23/00

    Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

    FLAT METAL FEATURES FOR MICROELECTRONICS APPLICATIONS
    190.
    发明申请
    FLAT METAL FEATURES FOR MICROELECTRONICS APPLICATIONS 有权

    公开(公告)号：US20210082754A1

    公开(公告)日：2021-03-18

    申请号：US17098128

    申请日：2020-11-13

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh

    IPC: H01L21/768 ,  H01L23/00 ,  H01L21/321

    Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

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