公开(公告)号：US09456500B2

公开(公告)日：2016-09-27

申请号：US13515012

申请日：2010-12-17

Applicant: Thomas Gottwald ,  Alexander Neumann

Inventor： Thomas Gottwald ,  Alexander Neumann

IPC: H05K3/30 ,  H05K1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H05K3/20 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/186 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/224 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/9202 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H05K1/189 ,  H05K3/205 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/462 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/10977 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83851

Abstract: The present invention relates to a method for producing a conductor structural element, comprising providing a rigid substrate, electrodepositing a copper coating on the rigid substrate, applying a conductor pattern structure to the copper coating, then possibly mounting components, laminating the substrate with at least one electrically insulating layer, detaching the rigid substrate, at least partially removing the remaining copper coating of the rigid substrate in such a way that the conductor pattern structure is exposed.

Abstract translation: 导体结构元件的制造方法技术领域本发明涉及一种导体结构元件的制造方法，其特征在于，提供刚性基板，在所述刚性基板上电沉积铜涂层，将铜导体图案结构施加到所述铜涂层上，然后可能安装部件，至少层叠所述基板 一个电绝缘层，分离刚性基板，至少部分地去除刚性基板的剩余的铜涂层，使得暴露导体图案结构。

公开(公告)号：US20160245933A1

公开(公告)日：2016-08-25

申请号：US14630968

申请日：2015-02-25

Applicant: Teledyne DALSA, Inc.

Inventor： Anton Petrus Maria van Arendonk

IPC: G01T7/00 ,  G01T1/24 ,  H05K3/32 ,  G01T1/20

CPC classification number: H05K1/117 ,  H01L24/01 ,  H05K3/3426 ,  H05K2201/10151 ,  H05K2201/10287 ,  H05K2201/10977

Abstract: Wirebond protection is provided for imaging tiles in which the imaging sensor and PCB are mounted side-by-side on a tile carrier for use in X or Gamma Ray indirect imaging detectors without use of a “glob top” encapsulant. A glass cap comprising a bead of adhesive material and a lid is formed to provide an enclosed open-air cavity around the wire bonds. As such, any expansion of the bead material does not produce mechanical stress on the wire bonds.

Abstract translation: 提供了用于成像瓦片的成像瓦片，其中成像传感器和PCB并排安装在瓦片载体上以用于X或伽马射线间接成像检测器，而不使用“球顶”密封剂。 形成包括粘合剂材料珠和盖的玻璃盖，以在引线接合周围提供封闭的露天空腔。 因此，珠粒材料的任何膨胀不会对引线接合产生机械应力。

公开(公告)号：US09414501B2

公开(公告)日：2016-08-09

申请号：US13829921

申请日：2013-03-14

Applicant: Board of Regents, The University of Texas System

Inventor： Ryan B. Wicker ,  Francisco Medina ,  Eric MacDonald ,  Danny W. Muse ,  David Espalin

IPC: H01K3/10 ,  H05K3/32 ,  H05K3/10 ,  H05K1/02 ,  H01L23/00

CPC classification number: H05K3/103 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/49175 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85214 ,  H01L2224/85238 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/181 ,  H05K1/0284 ,  H05K1/0296 ,  H05K3/321 ,  H05K3/328 ,  H05K3/34 ,  H05K2201/0129 ,  H05K2201/09036 ,  H05K2201/09681 ,  H05K2201/10977 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/049 ,  Y10T29/49155 ,  Y10T29/5193 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: The present invention provides systems and methods for creating interlayer mechanical or electrical attachments or connections using filaments within a three-dimensional structure, structural component, or structural electronic, electromagnetic or electromechanical component/device.

Abstract translation: 本发明提供用于在三维结构，结构部件或结构电子，电磁或机电部件/装置内使用细丝创建层间机械或电连接或连接的系统和方法。

公开(公告)号：US09360378B2

公开(公告)日：2016-06-07

申请号：US14395467

申请日：2013-04-03

Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (C.N.R.S.) ,  UNIVERSITE DE FRANCHE-COMTE

Inventor： Sylvain Ballandras ,  Bruno Francois

IPC: H05K7/00 ,  G01K11/26 ,  H05K1/02 ,  B23K1/00 ,  H05K1/18 ,  H05K3/28 ,  H05K1/03 ,  H05K1/05 ,  H05K3/10 ,  H05K3/34

CPC classification number: G01K11/265 ,  B23K1/0016 ,  B23K2101/38 ,  H01L2224/45014 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/8592 ,  H01L2924/181 ,  H05K1/0293 ,  H05K1/0306 ,  H05K1/053 ,  H05K1/181 ,  H05K3/103 ,  H05K3/285 ,  H05K3/3426 ,  H05K2201/1006 ,  H05K2201/10068 ,  H05K2201/10075 ,  H05K2201/10083 ,  H05K2201/10098 ,  H05K2201/10151 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2201/10977 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An electrical device includes a first electrical component and a second electrical component connected to each other via an electrical connection having an electrically insulating support plate and a weld joint deposited on the support plate. The weld joint has a melting temperature (Ta) significantly lower than an ambient operating temperature (Ta) to which at least one of the two electrical components and the electrical connection are subjected. The electrical device includes cement that completely covers the exposed weld joint. The material of the cement is chosen to maintain its adhesion and its tightness with respect to the weld joint when the Ta is applied.

Abstract translation: 电气设备包括通过电连接彼此连接的第一电气部件和第二电气部件，该电气连接具有电绝缘支撑板和沉积在支撑板上的焊接接头。 焊接接头具有明显低于两个电气部件和电连接中的至少一个所承受的环境工作温度（Ta）的熔化温度（Ta）。 电气设备包括完全覆盖暴露的焊接接头的水泥。 当施加Ta时，选择水泥的材料以保持其粘合性和相对于焊接接头的密封性。

公开(公告)号：US20160150632A1

公开(公告)日：2016-05-26

申请号：US14549934

申请日：2014-11-21

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： LAKSHMINARAYAN VISWANATHAN ,  AUDEL A. SANCHEZ ,  FERNANDO A. SANTOS ,  JERRY L. WHITE

IPC: H05K1/02 ,  H05K3/30 ,  H05K3/28 ,  H05K1/18

CPC classification number: H05K3/284 ,  H01L21/56 ,  H01L23/22 ,  H01L23/28 ,  H01L31/0203 ,  H01L31/048 ,  H01L33/52 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/73227 ,  H01L2224/73267 ,  H01L2224/92164 ,  H01L2224/92244 ,  H05K1/185 ,  H05K3/3421 ,  H05K9/0052 ,  H05K9/0081 ,  H05K2201/10166 ,  H05K2201/10371 ,  H05K2201/10977 ,  H05K2203/1316 ,  H05K2203/1327

Abstract: An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.

Abstract translation: 电子设备的实施例包括耦合到衬底的顶表面的电路部件（例如，晶体管或其他部件）。 在衬底和组件上形成封装。 封装中的开口从封装顶表面延伸到元件顶表面上的导电特征。 封装开口内的导电端接结构从导电特征延伸到封装顶表面。 器件还可以包括物理耦合到封装顶表面的第二电路，并且通过导电端接结构电耦合到部件。 在替代实施例中，导电端接结构可以位于封装中的沟槽中，该沟槽在嵌入封装内的两个电路之间延伸，其中导电端接结构被配置为在器件操作期间减小两个电路之间的电磁耦合。

公开(公告)号：US09326388B2

公开(公告)日：2016-04-26

申请号：US13950303

申请日：2013-07-25

Applicant: E Ink Holdings Inc.

Inventor： Lih-Hsiung Chan ,  Chu-Kuang Tseng

IPC: B29C65/52 ,  B32B37/12 ,  B32B43/00 ,  H05K3/32 ,  H05K1/18

CPC classification number: H05K3/323 ,  H05K1/189 ,  H05K2201/10136 ,  H05K2201/10977

Abstract: A flexible display apparatus including a flexible display panel, at least one flexible circuit board, at least one driving chip, and a sealing layer is provided. The flexible display panel has a display area and a bonding area located outside the display area. The flexible circuit board is disposed in the bonding area of the flexible display panel. The driving chip is disposed on the flexible circuit board. The sealing layer encapsulates a periphery of the flexible display panel and extendedly covers the bonding area and a portion of the flexible circuit board.

Abstract translation: 提供一种柔性显示装置，包括柔性显示面板，至少一个柔性电路板，至少一个驱动芯片和密封层。 柔性显示面板具有位于显示区域外的显示区域和结合区域。 柔性电路板设置在柔性显示面板的接合区域中。 驱动芯片设置在柔性电路板上。 密封层封装柔性显示面板的周边，并且延伸地覆盖柔性电路板的接合区域和一部分。

公开(公告)号：US20160099205A1

公开(公告)日：2016-04-07

申请号：US14845573

申请日：2015-09-04

Applicant: HEUNG KYU KWON ,  HAE GU LEE ,  BYEONG YEON CHO

Inventor： HEUNG KYU KWON ,  HAE GU LEE ,  BYEONG YEON CHO

IPC: H01L23/498 ,  H01L23/544 ,  G06F1/16 ,  H01L25/18 ,  H01L23/48 ,  H05K1/18 ,  H01L23/31 ,  H01L25/065

CPC classification number: G06F1/1601 ,  G06F1/16 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/16 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/54406 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H05K1/0269 ,  H05K3/3436 ,  H05K2201/10159 ,  H05K2201/10515 ,  H05K2201/10734 ,  H05K2201/10977 ,  H01L2224/81

Abstract: A semiconductor package includes a printed circuit board (PCB), a chip bonded to the PCB, a mold protecting the chip and exposing a backside surface of the chip, via openings extending in the mold to expose first contacts bonded to the PCB, and at least one first marking inscribed in a marking region of the mold between the backside surface of the chip and the vias. The mold has an exposed molded underfill (eMUF) structure covering the sides of the chip while exposing the backside surface of the chip. A PoP package includes a top package stacked on and electrically connected to the semiconductor package.

Abstract translation: 半导体封装包括印刷电路板（PCB），与PCB结合的芯片，通过在模具中延伸的开口来露出芯片背面的模具，以暴露出与PCB结合的第一触点，以及 在芯片的背面和通孔之间刻有刻在模具的标记区域中的至少一个第一标记。 模具具有暴露的模制底部填充（eMUF）结构，覆盖芯片的两侧同时暴露芯片的背面。 PoP封装包括堆叠在电连接到半导体封装上的顶部封装。

公开(公告)号：US09305908B2

公开(公告)日：2016-04-05

申请号：US14213342

申请日：2014-03-14

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Detlef Bernd Krabe ,  Josef Wittl

IPC: H01L21/56 ,  H01L31/0203 ,  H01L25/16 ,  H01L33/00 ,  H01L31/18 ,  H01L31/16 ,  H01L33/52 ,  H01S5/022 ,  H01S5/02 ,  H05K1/18

CPC classification number: H01L25/167 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/96 ,  H01L24/97 ,  H01L25/165 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/16 ,  H01L31/167 ,  H01L31/18 ,  H01L33/005 ,  H01L33/52 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/9222 ,  H01L2933/0033 ,  H01L2933/005 ,  H01S5/0201 ,  H01S5/02248 ,  H01S5/02272 ,  H05K1/181 ,  H05K2201/10121 ,  H05K2201/10727 ,  H05K2201/10977 ,  Y02P70/521

Abstract: Methods are provided for making embedded Wafer-Level Packaging (eWLP) devices, packages and assemblies. The eWLP methods allow back side electrical and/or thermal connections to be easily and economically made at the eWLP wafer level without having to use thru-mold vias (TMVs) or thru-silicon vias (TSVs) to make such connections. In order to create TMVs, processes such as reactive ion etching or laser drilling followed metallization are needed, which present difficulties and increase costs. In addition, the eWLP methods allow electrical and optical interfaces to be easily and economically formed on the front side and/or on the back side of the eWLP wafer, which allows the eWLP methods to be used to form optoelectronic devices having a variety of useful configurations.

Abstract translation: 提供了嵌入式晶圆级封装（eWLP）器件，封装和组件的方法。 eWLP方法允许在eWLP晶片级别容易且经济地进行背面电气和/或热连接，而不必使用通孔（TMV）或通硅硅通孔（TSV）来进行这种连接。 为了创建TMV，需要诸如反应离子蚀刻或激光钻孔等过程进行金属化处理，从而存在困难并增加成本。 此外，eWLP方法允许在eWLP晶片的前侧和/或背面容易且经济地形成电和光学界面，这允许eWLP方法形成具有各种有用的光电器件 配置

公开(公告)号：US09258890B2

公开(公告)日：2016-02-09

申请号：US14294875

申请日：2014-06-03

Applicant: STMicroelectronics, Inc.

Inventor： Rammil Seguido ,  Frederick Ray Gomez ,  Emmanuel Angeles

IPC: H01L23/52 ,  H01L23/48 ,  H05K1/02 ,  H05K3/30 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0296 ,  H01L23/66 ,  H01L25/0652 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/09236 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10719 ,  H05K2201/10977 ,  H05K2203/049 ,  Y10T29/49146 ,  H01L2924/00014

Abstract: Delamination of stacked integrated circuit die configurations on printed circuit boards is avoided by providing a metal trace support structure underneath the die stack. The metal trace support structure features substantially equally spaced thin metal traces in place of a contiguous metal plate which has been used in the past. Spaced apart thin metal traces are less vulnerable to thermal expansion than a metal plate which has a large thermal mass. The metal traces still provide structural stability, while preventing delamination of the die stack configuration during thermal processing. A method of attaching a bridge die stack configuration to a printed circuit board by adhering a die attach film to a field of metal traces is demonstrated. In addition, the electrical and structural integrity of the bridge die stack formed with a metal trace support structure is confirmed with test results.

Abstract translation: 通过在管芯堆叠下方提供金属迹线支撑结构，可以避免印刷电路板上的堆叠集成电路管芯结构的分层。 金属迹线支撑结构具有基本相等间隔的细金属迹线，代替过去使用的连续金属板。 分隔开的薄金属迹线比具有大热质量的金属板不易受热膨胀。 金属迹线仍然提供结构稳定性，同时防止热处理期间芯片堆叠配置的分层。 证明了通过将管芯附着膜粘附到金属痕迹的领域将桥模组叠构造附着到印刷电路板的方法。 此外，用测试结果证实了由金属迹线支撑结构形成的桥模组的电气和结构完整性。

公开(公告)号：US09226400B2

公开(公告)日：2015-12-29

申请号：US13734266

申请日：2013-01-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masato Nomiya ,  Norio Sakai ,  Mitsuyoshi Nishide

IPC: H05K1/03 ,  H05K1/00 ,  H05K1/16 ,  H01R4/58 ,  H05K7/10 ,  H05K1/18 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15 ,  H01L23/498 ,  H01L23/00 ,  H05K3/30 ,  H05K3/46

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K3/305 ,  H05K3/4626 ,  H05K3/4629 ,  H05K2201/0116 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/1147 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: In a method for manufacturing a multilayer ceramic electronic device, a multilayer ceramic element assembly including laminated unsintered ceramic base material layers, a first conductor pattern, a seat portion disposed in a surface of the multilayer ceramic element assembly and arranged to mount a surface mount electronic device thereon, a second conductor pattern connected to the surface mount electronic device, and a resin introduction portion located outside a vertically projected region of the surface mount electronic device and arranged to introduce a resin to the seat portion is prepared. The multilayer ceramic element assembly is fired and the surface mount electronic device is mounted on the seat portion of the fired multilayer ceramic element assembly with the second conductor pattern therebetween. The resin is filled from the resin introduction portion into the seat portion and between the seat portion and the surface mount electronic device and is cured.

Abstract translation: 在多层陶瓷电子器件的制造方法中，包括层叠的未烧结的陶瓷基材层的多层陶瓷元件组件，第一导体图案，配置在所述多层陶瓷元件组件的表面的座部， 设置在其上，连接到表面安装电子设备的第二导体图案，以及位于表面安装电子设备的垂直投影区域外部并且布置成将树脂引入座部的树脂引入部分。 烧结多层陶瓷元件组件，并且表面安装电子器件安装在烧制的多层陶瓷元件组件的座部上，其间具有第二导体图案。 树脂从树脂引入部分填充到座椅部分中，并且在座椅部分和表面安装电子装置之间填充并固化。