公开(公告)号：US08957323B2

公开(公告)日：2015-02-17

申请号：US13973900

申请日：2013-08-22

申请人： National Chiao Tung University

发明人： Chih Chen ,  Wei-Lan Chiu

IPC分类号： H05K3/02 ,  H05K1/11 ,  H05K1/09 ,  H05K3/40

CPC分类号： H05K1/09 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81948 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15787 ,  H01L2924/3651 ,  H01L2924/3656 ,  H05K3/40 ,  Y10T29/49149 ,  Y10T29/49155 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/81805

摘要： An electrical connecting element, a method of fabricating the same, and an electrical connecting structure comprising the same are disclosed. The method of fabricating the electrical connecting structure having twinned copper of the present invention comprises steps of: (A) providing a first substrate; (B) forming a nano-twinned copper layer on part of a surface of the first substrate; (C) forming a solder on the nano-twinned copper layer of the first substrate; and (D) reflowing the nano-twinned Cu layer and solder to produce a solder joint, wherein at least part of the solder reacts with the nano-twinned copper layer to produce an intermetallic compound (IMC) layer which comprises a Cu3Sn layer, This invention reduces the voids formation in the interface between the intermetallic compound and the solder, and then enhances the reliability of solder joints.

摘要翻译： 公开了电连接元件，其制造方法和包括该电连接元件的电连接结构。 本发明的制造具有双绞铜的电连接结构的方法包括以下步骤：（A）提供第一衬底; （B）在所述第一基板的一部分表面上形成纳米双晶铜层; （C）在第一基板的纳米双晶铜层上形成焊料; 和（D）回流纳米双晶Cu层和焊料以产生焊接接头，其中焊料的至少一部分与纳米双晶铜层反应产生包含Cu 3 Sn层的金属间化合物（IMC）层。 本发明减少了金属间化合物和焊料之间的界面中形成的空隙，从而提高了焊点的可靠性。

公开(公告)号：US20140318838A1

公开(公告)日：2014-10-30

申请号：US14330882

申请日：2014-07-14

申请人： Samsung Electro-Mechanics Co., Ltd.

发明人： Myung Whun CHANG ,  Dae Hyeong LEE ,  Ki Pyo HONG

IPC分类号： H05K1/11 ,  G01R1/02

CPC分类号： H05K1/11 ,  G01R1/02 ,  H05K1/09 ,  H05K3/225 ,  H05K3/4015 ,  H05K3/4061 ,  Y10T29/49002 ,  Y10T29/49149 ,  Y10T29/49165 ,  Y10T29/49726 ,  Y10T29/49748

摘要： There is provided a method of repairing a probe board, the method including: preparing a plurality of first via electrodes filled with a first filling material in a board body formed as a ceramic sintered body; forming a via hole for an open via electrode among the plurality of first via electrodes; filling the via hole with a second filling material having a lower sintering temperature than that of the first filling material; and forming a second via electrode by sintering the second filling material. The open via repair according to the present invention improves the manufacturing yield of the board and reduces the manufacturing costs thereof.

摘要翻译： 提供了一种修复探针板的方法，所述方法包括：在形成为陶瓷烧结体的板体中制备多个填充有第一填充材料的第一通孔电极; 在所述多个第一通孔电极中形成用于开放通孔电极的通孔; 用具有比第一填充材料低的烧结温度的第二填充材料填充通孔; 以及通过烧结所述第二填充材料形成第二通孔电极。 根据本发明的开放通孔修复提高了板的制造成品率并降低了其制造成本。

公开(公告)号：US20140317919A1

公开(公告)日：2014-10-30

申请号：US14323728

申请日：2014-07-03

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Jin Su KIM ,  Seog Moon CHOI

IPC分类号： H05K3/34

CPC分类号： H05K3/3457 ,  H01L21/4853 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/0052 ,  H05K3/3478 ,  H05K2203/0405 ,  Y10T29/49128 ,  Y10T29/49135 ,  Y10T29/4914 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49169 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： Embodiments of the invention provide a method of manufacturing a printed circuit board. The method includes the steps of mounting a strip substrate on a fixing member, and separating the strip substrate into unit substrates by performing a singulation process. The method further includes the steps of attaching solder balls onto the unit substrates using a mask disposed on the unit substrates, and fixing the solder balls on the unit substrates by performing a reflow process.

摘要翻译： 本发明的实施例提供一种制造印刷电路板的方法。 该方法包括以下步骤：将带状基材安装在固定部件上，并通过执行切割处理将带状基板分离成单元基板。 该方法还包括使用设置在单元基板上的掩模将焊球附着到单元基板上的步骤，以及通过进行回流处理将焊球固定在单元基板上。

公开(公告)号：US20140300382A1

公开(公告)日：2014-10-09

申请号：US14082528

申请日：2013-11-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Martin ECKERT ,  Eckhard KUNIGKEIT ,  Otto A. TORREITER ,  Quintino L. TRIANNI

IPC分类号： G01R31/28

CPC分类号： G01R31/2886 ,  G01R31/2896 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/13 ,  H05K3/325 ,  H05K3/341 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49149

摘要： A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.

摘要翻译： 描述了一种用于3-D集成电路芯片堆栈的电测试的方法。 3-D集成电路芯片堆叠至少包括第一集成电路芯片和第二集成电路芯片。 第一集成电路芯片和第二集成电路芯片不被焊接在一起用于进行电气测试。

公开(公告)号：US08836136B2

公开(公告)日：2014-09-16

申请号：US13405108

申请日：2012-02-24

申请人： Ellis Chau ,  Reynaldo Co ,  Roseann Alatorre ,  Philip Damberg ,  Wei-Shun Wang ,  Se Young Yang ,  Zhijun Zhao

发明人： Ellis Chau ,  Reynaldo Co ,  Roseann Alatorre ,  Philip Damberg ,  Wei-Shun Wang ,  Se Young Yang ,  Zhijun Zhao

IPC分类号： H01L23/48

CPC分类号： H01L24/85 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49517 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/16 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48997 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/851 ,  H01L2224/8518 ,  H01L2224/85399 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1715 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y10T29/49149 ,  Y10T29/49151 ,  H01L2224/45664 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

摘要： A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.

摘要翻译： 微电子封装可以包括引线键合，其具有结合到衬底上的相应导电元件的底部并且与基底相对的端部。 从衬底延伸的电介质封装层覆盖引线接合的部分，使得引线键合的被覆部分通过封装层彼此分离，其中引线键合的未封装部分由未被覆盖的引线键的部分限定 通过封装层。 未封装的部分可以布置在具有最小间距的图案的位置处，该最小间距大于相邻引线键的基部之间的第一最小间距。

公开(公告)号：US08806731B2

公开(公告)日：2014-08-19

申请号：US12987697

申请日：2011-01-10

申请人： Myung Whun Chang ,  Dae Hyeong Lee ,  Ki Pyo Hong

发明人： Myung Whun Chang ,  Dae Hyeong Lee ,  Ki Pyo Hong

IPC分类号： B23P6/00

CPC分类号： H05K1/11 ,  G01R1/02 ,  H05K1/09 ,  H05K3/225 ,  H05K3/4015 ,  H05K3/4061 ,  Y10T29/49002 ,  Y10T29/49149 ,  Y10T29/49165 ,  Y10T29/49726 ,  Y10T29/49748

摘要： There is provided a method of repairing a probe board, the method including: preparing a plurality of first via electrodes filled with a first filling material in a board body formed as a ceramic sintered body; forming a via hole for an open via electrode among the plurality of first via electrodes; filling the via hole with a second filling material having a lower sintering temperature than that of the first filling material; and forming a second via electrode by sintering the second filling material. The open via repair according to the present invention improves the manufacturing yield of the board and reduces the manufacturing costs thereof.

摘要翻译： 提供了一种修复探针板的方法，所述方法包括：在形成为陶瓷烧结体的板体中制备多个填充有第一填充材料的第一通孔电极; 在所述多个第一通孔电极中形成用于开放通孔电极的通孔; 用具有比第一填充材料低的烧结温度的第二填充材料填充通孔; 以及通过烧结所述第二填充材料形成第二通孔电极。 根据本发明的开放通孔修复提高了板的制造成品率并降低了其制造成本。

公开(公告)号：US20140223733A1

公开(公告)日：2014-08-14

申请号：US13764794

申请日：2013-02-12

申请人： Joseph Lai

发明人： Joseph Lai

IPC分类号： H01R43/20

CPC分类号： H01R43/24 ,  H01R24/62 ,  H01R2107/00 ,  H05K1/00 ,  H05K2203/0165 ,  Y10T29/49149 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/4921 ,  Y10T29/49211

摘要： A new method for making and manufacturing the User-Friendly USB Male connectors which is faster, lower cost, more energy efficient, waterproof and reliable, with no expensive tooling and molding required, having better quality and being easily adaptable for automated assembly.

摘要翻译： 一种制造和制造用户友好的USB公连接器的新方法，其更快，更低的成本，更节能，防水和可靠，不需要昂贵的模具和成型，具有更好的质量并且易于适应于自动组装。

公开(公告)号：US08800140B2

公开(公告)日：2014-08-12

申请号：US12986081

申请日：2011-01-06

申请人： Jamille F. Hetke ,  Daryl R. Kipke ,  David S. Pellinen ,  David J. Anderson

发明人： Jamille F. Hetke ,  Daryl R. Kipke ,  David S. Pellinen ,  David J. Anderson

IPC分类号： H05K3/02

CPC分类号： A61B5/04001 ,  A61B2562/0209 ,  A61B2562/043 ,  A61N1/0534 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49211

摘要： Some embodiments of the invention comprise a customizable multichannel microelectrode array with a modular planar microfabricated electrode array attached to a carrier and a high density of recording and/or stimulation electrode sites disposed thereon. Novel methods of making and using same are also disclosed.

摘要翻译： 本发明的一些实施例包括可定制的多通道微电极阵列，其具有连接到载体的模块化平面微加工电极阵列和设置在其上的高密度记录和/或刺激电极位置。 还公开了制备和使用它们的新方法。

公开(公告)号：US20140202739A1

公开(公告)日：2014-07-24

申请号：US14221431

申请日：2014-03-21

申请人： FUJITSU LIMITED

发明人： Taiji Sakai ,  Seiki Sakuyama

IPC分类号： H05K1/02 ,  H05K13/04

CPC分类号： H05K1/0298 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/81097 ,  H01L2224/81815 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/30105 ,  H05K3/3436 ,  H05K3/3473 ,  H05K13/0465 ,  H05K2201/10674 ,  H05K2203/072 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49139 ,  Y10T29/49149 ,  Y10T29/49155

摘要： A printed wiring board includes a Cu wiring pattern formed on a substrate. A first metal layer is formed on the Cu wiring pattern. A second metal layer is formed on the first metal layer. The first metal layer has a less reactivity with Cu than the second metal layer. The first metal layer and the second metal layer together cause an eutectic reaction.

摘要翻译： 印刷电路板包括形成在基板上的Cu布线图案。 在Cu布线图案上形成第一金属层。 在第一金属层上形成第二金属层。 第一金属层与Cu的反应性比第二金属层低。 第一金属层和第二金属层一起引起共晶反应。

公开(公告)号：US08752284B2

公开(公告)日：2014-06-17

申请号：US12047552

申请日：2008-03-13

申请人： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

发明人： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC分类号： H01R9/00 ,  H05K3/00

CPC分类号： H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

摘要： A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

摘要翻译： 一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触 飞机