公开(公告)号：US08962392B2

公开(公告)日：2015-02-24

申请号：US13418868

申请日：2012-03-13

Applicant: Chin-Fu Kao ,  Jing-Cheng Lin ,  Jui-Pin Hung ,  Szu Wei Lu

Inventor： Chin-Fu Kao ,  Jing-Cheng Lin ,  Jui-Pin Hung ,  Szu Wei Lu

IPC: H01L21/50 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/568 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die.

Abstract translation: 一种方法包括将载体粘合在顶模上。 该方法还包括固化设置在基底和顶模之间的底部填充物。 该方法还包括在固化期间在载体上施加力。 该方法还包括从顶模移除载体。

公开(公告)号：US08928159B2

公开(公告)日：2015-01-06

申请号：US12874952

申请日：2010-09-02

Applicant: Hsin Chang ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

Inventor： Hsin Chang ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L21/683 ,  H01L21/768 ,  H01L23/544 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00

Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

Abstract translation: 一种器件包括衬底和包括穿透衬底的导电贯穿衬底通孔（TSV）的对准标记。

公开(公告)号：US08872326B2

公开(公告)日：2014-10-28

申请号：US13597868

申请日：2012-08-29

Applicant: Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

IPC: H01L23/48

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/27 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00011

Abstract: The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure.

Abstract translation: 上述形成半导体器件封装的机构由于相对简单的工艺流程而提供了低成本的制造工艺。 通过形成具有再分布层的互连结构以使得能够在封装结构下方的一个或多个管芯接合，整体封装的翘曲大大降低。 此外，形成互连结构，而不使用模塑料，这减少了颗粒污染。 翘曲和颗粒污染的减少会提高产量。 此外，形成的半导体器件封装具有低的形状因数，其中一个或多个管芯装配在封装结构和互连结构之间的空间的下方。

公开(公告)号：US08772945B2

公开(公告)日：2014-07-08

申请号：US13457841

申请日：2012-04-27

Applicant: Yung-Chi Lin ,  Wen-Chih Chiou ,  Yen-Hung Chen ,  Sylvia Lo ,  Jing-Cheng Lin

Inventor： Yung-Chi Lin ,  Wen-Chih Chiou ,  Yen-Hung Chen ,  Sylvia Lo ,  Jing-Cheng Lin

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05541 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05552

Abstract: A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like.

Abstract translation: 公开了一种用于向TSV提供沉积在TSV的顶表面下方的阻挡层的系统和方法，顶表面具有减小的地形变化。 将底部TSV焊盘沉积到通孔中，然后抛光，使得顶表面在衬底顶表面下方。 然后在通孔中沉积阻挡层，并且沉积在阻挡层上的顶部TSV焊盘。 顶部的TSV屏障垫被抛光，以使顶部TSV焊盘的顶部表面与衬底的高度一致。 阻挡垫可以小于约1微米厚，并且顶部TSV垫可以小于约6微米厚。 阻挡垫可以是来自顶部和底部TSV垫的不同金属，并且可以选自包括钛，钽，钴，镍等的组。

公开(公告)号：US20140061897A1

公开(公告)日：2014-03-06

申请号：US13624356

申请日：2012-09-21

Applicant: Jing-Cheng Lin ,  Po-Hao Tsai

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/498 ,  H01L21/28

CPC classification number: H01L24/11 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/06102 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11612 ,  H01L2224/11614 ,  H01L2224/1182 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/14155 ,  H01L2224/14156 ,  H01L2224/14177 ,  H01L2224/14515 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16168 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01108 ,  H01L2224/11 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/00

Abstract: A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar.

Abstract translation: 封装结构包括通过将第一基板上的金属柱连接到第二基板上的连接器而将第一基板接合到第二基板。 第一金属柱形成在第一衬底的第一区域上并覆盖并电连接到金属焊盘，第二金属柱形成在第一衬底的第二区域中的钝化层上。 在金属柱和第一连接器之间形成第一焊接区域，在第二金属柱和第二连接器之间形成第二焊点区域。 第一金属柱的厚度大于第二金属柱的厚度。

公开(公告)号：US20140061888A1

公开(公告)日：2014-03-06

申请号：US13597868

申请日：2012-08-29

Applicant: Jing-Cheng LIN ,  Chin-Chuan CHANG ,  Jui-Pin HUNG

Inventor： Jing-Cheng LIN ,  Chin-Chuan CHANG ,  Jui-Pin HUNG

IPC: H01L23/02 ,  H01L21/50

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/27 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00011

Abstract: The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure.

Abstract translation: 上述形成半导体器件封装的机构由于相对简单的工艺流程而提供了低成本的制造工艺。 通过形成具有再分布层的互连结构以使得能够在封装结构下方的一个或多个管芯接合，整体封装的翘曲大大降低。 此外，形成互连结构，而不使用模塑料，这减少了颗粒污染。 翘曲和颗粒污染的减少会提高产量。 此外，形成的半导体器件封装具有低的形状因数，其中一个或多个管芯装配在封装结构和互连结构之间的空间的下方。

公开(公告)号：US08664760B2

公开(公告)日：2014-03-04

申请号：US13343582

申请日：2012-01-04

Applicant: Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Cheng-Chieh Hsieh ,  Kuo-Ching Hsu ,  Ying-Ching Shih ,  Po-Hao Tsai ,  Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Cheng-Chieh Hsieh ,  Kuo-Ching Hsu ,  Ying-Ching Shih ,  Po-Hao Tsai ,  Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/11 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/04 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10145 ,  H01L2224/10156 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13578 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/3651 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/00

Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

公开(公告)号：US20140027872A1

公开(公告)日：2014-01-30

申请号：US13558063

申请日：2012-07-25

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Jing-Cheng Lin

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L27/14689 ,  H01L21/6835 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02002 ,  H01L31/02327 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/023 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL.

Abstract translation: 一种器件包括半导体衬底，在半导体衬底的前表面处的图像传感器和图像传感器上的多个电介质层。 滤色器和微透镜设置在多个介电层上并与图像传感器对准。 穿通通孔穿过半导体衬底。 再分配线（RDL）设置在多个介电层上，其中RDL电连接到通孔。 聚合物层覆盖RDL。

公开(公告)号：US20140001645A1

公开(公告)日：2014-01-02

申请号：US13619877

申请日：2012-09-14

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/50 ,  H01L21/56 ,  H01L21/58

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14134 ,  H01L2224/14144 ,  H01L2224/14154 ,  H01L2224/14164 ,  H01L2224/14181 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position.

Abstract translation: 提供了一种三维堆叠半导体器件的系统和方法。 在一个实施例中，将两个或更多个半导体管芯附着到载体并封装。 两个或更多个半导体管芯的连接被暴露，并且两个或更多个半导体管芯可以被薄化以在相对侧上形成连接。 然后可以将另外的半导体管芯置于偏移或悬垂位置中。

公开(公告)号：US08610285B2

公开(公告)日：2013-12-17

申请号：US13298046

申请日：2011-11-16

Applicant: Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Kuo-Ching Hsu ,  Cheng-Chieh Hsieh ,  Ying-Ching Shih ,  Po-Hao Tsai ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Kuo-Ching Hsu ,  Cheng-Chieh Hsieh ,  Ying-Ching Shih ,  Po-Hao Tsai ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L24/11 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/04 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10145 ,  H01L2224/10156 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13578 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/3651 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/00

Abstract: A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Abstract translation: 封装组件不含其中的有源器件。 封装部件包括衬底，衬底中的通孔，衬底上的顶部电介质层，以及在顶部电介质层的顶表面上方具有顶表面的金属柱。 金属柱电连接到通孔。 扩散阻挡层在金属支柱的上表面之上。 焊料帽设置在扩散阻挡层上。