公开(公告)号：US10475759B2

公开(公告)日：2019-11-12

申请号：US13270776

申请日：2011-10-11

申请人： Shin-Puu Jeng ,  Chen-Hua Yu ,  Jing-Cheng Lin

发明人： Shin-Puu Jeng ,  Chen-Hua Yu ,  Jing-Cheng Lin

IPC分类号： H01L23/488 ,  H01L25/11 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

摘要： An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors.

公开(公告)号：US09768105B2

公开(公告)日：2017-09-19

申请号：US13452589

申请日：2012-04-20

申请人： Mirng-Ji Lii ,  Chen-Hua Yu ,  Chien-Hsiun Lee ,  Yung Ching Chen ,  Jiun Yi Wu

发明人： Mirng-Ji Lii ,  Chen-Hua Yu ,  Chien-Hsiun Lee ,  Yung Ching Chen ,  Jiun Yi Wu

IPC分类号： H01L25/07 ,  H01L21/60 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/528 ,  H01L25/10

CPC分类号： H01L23/49838 ,  H01L23/49811 ,  H01L23/5283 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/00014 ,  H01L2924/00

摘要： System and method are disclosed for creating a rigid interconnect between two substrate mounted packages to create a package-on-package assembly. A solid interconnect may have a predetermined length configured to provide a predetermined package separation, may be cylindrical, conical or stepped, may be formed by extrusion, casting, drawing or milling and may have an anti-oxidation coating. The interconnect may be attached to mounting pads on the top and bottom packages via an electrically conductive adhesive, including, but not limited to solder and solder paste. A solder preservative or other anti-oxidation coating may be applied to the mounting pad. A package-on-package assembly with solid interconnects may have a top package configured to accept at least one electronic device, with the solid interconnects mounted between the top package and a bottom package to rigidly hold the package about parallel to each other.

公开(公告)号：US09679783B2

公开(公告)日：2017-06-13

申请号：US13208197

申请日：2011-08-11

申请人： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： B29C33/12 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L21/561 ,  B29C33/123 ,  H01L21/566 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.

公开(公告)号：US09177843B2

公开(公告)日：2015-11-03

申请号：US11771734

申请日：2007-06-29

申请人： Chien-Ming Sung ,  Simon Wang ,  Jia-Ren Chen ,  Henry Lo ,  Chen-Hua Yu ,  Jean Wang ,  Kewei Zuo

发明人： Chien-Ming Sung ,  Simon Wang ,  Jia-Ren Chen ,  Henry Lo ,  Chen-Hua Yu ,  Jean Wang ,  Kewei Zuo

IPC分类号： H01L21/677 ,  H01L21/673 ,  H01L21/67

CPC分类号： H01L21/67393 ,  H01L21/67017 ,  H01L21/67161 ,  H01L21/67703 ,  Y10S414/139

摘要： A semiconductor manufacturing line includes an inert environment selected from the group consisting essentially of an inert airtight wafer holder, an inert wafer transport channel, an inert production tool, an inert clean room, and combinations thereof.

摘要翻译： 半导体生产线包括从基本上由惰性气密晶片保持器，惰性晶片输送通道，惰性生产工具，惰性洁净室及其组合组成的组中选择的惰性环境。

公开(公告)号：US08946742B2

公开(公告)日：2015-02-03

申请号：US12897124

申请日：2010-10-04

申请人： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

发明人： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

IPC分类号： H01L33/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/48 ,  H01L33/48 ,  H01L33/64 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498 ,  H01L23/00 ,  H01L33/62

CPC分类号： H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.

摘要翻译： 具有上述通孔硅衬底（或通孔）的基板消除了对导电凸块的需要。 流程非常简单，成本效益高。 所描述的结构将单独的TSV，再分配层和导电凸块结构组合成单个结构。 通过组合单独的结构，产生具有高散热能力的低电阻电连接。 此外，具有通过硅插头（或通孔或沟槽）的基板还允许将多个芯片封装在一起。 通过硅沟槽可围绕一个或多个芯片，以在制造期间提供防止铜扩散到相邻器件的保护。 此外，具有相似或不同功能的多个芯片可以集成在TSV基板上。 通过具有不同图案的硅插头可以在半导体芯片下使用以改善散热并解决制造问题。

公开(公告)号：US08941239B2

公开(公告)日：2015-01-27

申请号：US13586676

申请日：2012-08-15

申请人： Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

发明人： Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

IPC分类号： H01L23/48 ,  H01L21/14

CPC分类号： H01L21/76871 ,  H01L21/76846 ,  H01L2221/1089

摘要： A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier layer is conformally deposited on the sidewalls and the bottom of the opening. A first seed layer is conformally deposited on the first barrier layer. A second barrier layer is conformally deposited on the first seed layer. A second seed layer is conformally deposited on the second barrier layer and a conductive plug is deposited in the opening of the dielectric layer.

摘要翻译： 一种半导体器件中的铜互连结构，包括形成在半导体器件的电介质层中的开口，该开口具有侧壁和底部。 第一阻挡层保形地沉积在开口的侧壁和底部上。 第一种子层共形沉积在第一阻挡层上。 第二阻挡层被共形沉积在第一籽晶层上。 第二种子层被共形沉积在第二阻挡层上，并且导电塞被沉积在电介质层的开口中。

公开(公告)号：US08912651B2

公开(公告)日：2014-12-16

申请号：US13397747

申请日：2012-02-16

申请人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Chung-Shi Liu ,  Ming-Da Cheng

发明人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Chung-Shi Liu ,  Ming-Da Cheng

IPC分类号： H01L23/498

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/038 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05693 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/1184 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1358 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48693 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48793 ,  H01L2224/48811 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48893 ,  H01L2224/73204 ,  H01L2224/81009 ,  H01L2224/81026 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/01006

摘要： Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

摘要翻译： 实施例涉及包装封装（PoP）结构，包括柱状灯泡和形成PoP结构的方法。 根据实施例，结构包括第一基板，螺柱灯泡，模具，第二基板和电连接器。 螺柱灯泡耦合到第一基板的第一表面。 模具附接到第一基板的第一表面。 电连接器耦合到第二基板，并且相应的电连接器耦合到相应的螺柱灯泡。

公开(公告)号：US08841773B2

公开(公告)日：2014-09-23

申请号：US13608456

申请日：2012-09-10

申请人： Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00 ,  H01L23/525

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/525 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68359 ,  H01L2224/13022 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/14181 ,  H01L2924/01019 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

摘要翻译： 提供了用于堆叠管芯配置的多层互连结构。 在半导体衬底中形成贯通衬底通孔。 将半导体衬底的背面变薄以暴露通过衬底的通孔。 在半导体衬底的背面和贯通衬底通孔的暴露部分之后形成隔离膜。 第一导电元件被形成为电耦合到贯穿衬底通孔中的相应通孔并且在隔离膜上延伸。 可以形成一个或多个附加层的隔离膜和导电元件，其中诸如焊球的连接元件电耦合到最上面的导电元件。

公开(公告)号：US08797057B2

公开(公告)日：2014-08-05

申请号：US13025931

申请日：2011-02-11

申请人： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

发明人： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC分类号： G01R31/00

CPC分类号： G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

摘要： Test structures for performing electrical tests of devices under one or more microbumps are provided. Each test structure includes at least one microbump pad and a test pad. The microbump pad is a part of a metal pad connected to an interconnect for a device. A width of the microbump pad is equal to or less than about 50 μm. The test pad is connected to the at least one microbump pad. The test pad has a size large enough to allow circuit probing of the device. The test pad is another part of the metal pad. A width of the test pad is greater than the at least one microbump pad.

摘要翻译： 提供用于对一个或多个微丸下的装置进行电测试的测试结构。 每个测试结构包括至少一个微型块和测试垫。 微型焊盘是与设备的互连件连接的金属焊盘的一部分。 微型焊盘的宽度等于或小于约50μm。 测试垫连接到至少一个微型块。 测试垫的尺寸足够大以允许设备的电路探测。 测试垫是金属垫的另一部分。 测试垫的宽度大于至少一个微小块垫。

公开(公告)号：US08796132B2

公开(公告)日：2014-08-05

申请号：US13539188

申请日：2012-06-29

申请人： Ming-Chung Sung ,  Yung Ching Chen ,  Chien-Hsun Lee ,  Chen-Hua Yu ,  Mirng-Ji Lii

发明人： Ming-Chung Sung ,  Yung Ching Chen ,  Chien-Hsun Lee ,  Chen-Hua Yu ,  Mirng-Ji Lii

IPC分类号： H01L21/60 ,  H01L21/48

CPC分类号： H01L21/4825 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/742 ,  H01L24/78 ,  H01L2224/1134 ,  H01L2224/45144 ,  H01L2224/742 ,  H01L2224/78 ,  H01L2224/78301 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00

摘要： Disclosed herein is a system and method for mounting semiconductor packages by forming one or more interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a target package. Mounting the interconnect may comprise ultrasonically welding the interconnects to the mounting pads, and the interconnect may be mounted via a mounting node on the end of the interconnect, wherein the mounting node may be formed by an electric flame off process. The interconnects may be trimmed to one or more substantially uniform heights, optionally using a laser or contact-type trimming system, and the tails of the interconnects may be supported during trimming. A top package may be bonded on the trimmed ends of the interconnects. During mounting, a support plate may be used to support the package, and a mask maybe used during interconnect mounting.

摘要翻译： 本文公开了一种用于通过形成一个或多个互连件，可选地用引线键合器安装半导体封装以及将互连件安装到目标封装上的安装焊盘来安装半导体封装件的系统和方法。 安装互连可以包括将互连件超声波焊接到安装焊盘，并且互连可以经由互连端部上的安装节点来安装，其中安装节点可以由电火焰熄灭工艺形成。 互连可以被修剪到一个或多个基本均匀的高度，可选地使用激光或接触式修剪系统，并且在修剪期间可以支撑互连的尾部。 顶部封装可以结合在互连件的修剪端上。 在安装期间，可以使用支撑板来支撑封装，并且在互连安装期间可以使用掩模。