公开(公告)号：US08729685B2

公开(公告)日：2014-05-20

申请号：US13318205

申请日：2010-04-30

申请人： Thorbjörn Ebefors ,  Edward Kälvesten ,  Niklas Svedin ,  Anders Eriksson

发明人： Thorbjörn Ebefors ,  Edward Kälvesten ,  Niklas Svedin ,  Anders Eriksson

IPC分类号： H01L23/06

CPC分类号： H01L23/10 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13144 ,  H01L2224/29035 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/83805 ,  H01L2224/9211 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/0401

摘要： A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.

公开(公告)号：US20140035167A1

公开(公告)日：2014-02-06

申请号：US13954346

申请日：2013-07-30

申请人： Robert Bosch GmbH

发明人： Christoph Schelling ,  David Borowsky

IPC分类号： H01L21/48 ,  H01L23/48

CPC分类号： H01L21/4814 ,  B81B7/007 ,  B81B2207/095 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L23/48 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08148 ,  H01L2224/08221 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/13008 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/27825 ,  H01L2224/29011 ,  H01L2224/29023 ,  H01L2224/29035 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29564 ,  H01L2224/2957 ,  H01L2224/29647 ,  H01L2224/3003 ,  H01L2224/30051 ,  H01L2224/33517 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8183 ,  H01L2224/83011 ,  H01L2224/83013 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/8383 ,  H01L2224/9211 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01013 ,  H01L2924/04941 ,  H01L2924/04953

摘要： A method produces a bonding pad for thermocompression bonding. The method includes providing a carrier material having semiconductor structures, wherein an outermost edge layer of the carrier material is a wiring metal layer configured to make electrical contact with the semiconductor structures. The method also includes depositing a single-layered bonding metal layer directly on a surface of the wiring metal layer to produce the bonding pad.

摘要翻译： 一种方法产生用于热压接的接合焊盘。 该方法包括提供具有半导体结构的载体材料，其中载体材料的最外边缘层是配置为与半导体结构电接触的布线金属层。 该方法还包括在布线金属层的表面上直接沉积单层结合金属层以产生接合焊盘。

公开(公告)号：US20120292787A1

公开(公告)日：2012-11-22

申请号：US13334366

申请日：2011-12-22

申请人： Jong Hyun NAM

发明人： Jong Hyun NAM

IPC分类号： H01L23/48

CPC分类号： H01L29/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/14155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17106 ,  H01L2224/17181 ,  H01L2224/29034 ,  H01L2224/29035 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32106 ,  H01L2224/32111 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/33051 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

摘要： A stacked semiconductor package includes a substrate having an upper surface and a lower surface, and divided into a first region and a second region that adjoins the first region; a support member formed in the second region on the upper surface of the substrate; and a semiconductor chip module including a plurality of semiconductor chips each of which has bonding pads near one edge of a first surface thereof and which are stacked on the support member in a step-like shape such that their bonding pads face the first region and are bent such that the bonding pads are electrically connected with the substrate.

摘要翻译： 堆叠的半导体封装包括具有上表面和下表面的基板，并且被分成与第一区域相邻的第一区域和第二区域; 支撑构件，形成在所述基板的上表面上的所述第二区域中; 以及包括多个半导体芯片的半导体芯片模块，每个半导体芯片在其第一表面的一个边缘附近具有接合焊盘，并且以阶梯状形式堆叠在支撑构件上，使得它们的焊盘面向第一区域并且是 弯曲，使得焊盘与基板电连接。

公开(公告)号：US20120199960A1

公开(公告)日：2012-08-09

申请号：US13022146

申请日：2011-02-07

申请人： GLENN ENRICK CALDERON COSUE ,  EDGARDO RULLODA HORTALEZA ,  GERARDO CALDERON ANGELES ,  TIMER DEREQUITO PORRAS

发明人： GLENN ENRICK CALDERON COSUE ,  EDGARDO RULLODA HORTALEZA ,  GERARDO CALDERON ANGELES ,  TIMER DEREQUITO PORRAS

IPC分类号： H01L23/498 ,  H01L21/28

CPC分类号： H01L24/16 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/1134 ,  H01L2224/13082 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/1624 ,  H01L2224/29035 ,  H01L2224/29099 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73213 ,  H01L2224/73215 ,  H01L2224/811 ,  H01L2224/85205 ,  H01L2224/92143 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15787 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

摘要： An integrated circuit (IC) device includes an interposer having a dielectric substrate having a first side, a second side, and an inner aperture, wherein a plurality of electrically conductive traces are on the first side. An IC die includes a topside semiconductor surface having active circuitry and a bottomside surface, wherein the topside semiconductor surface includes a plurality of bond pads, and is attached over the inner aperture onto the interposer. First wirebond interconnects couple respective bond pads to respective electrically conductive traces. A workpiece includes a top workpiece surface including a plurality of contact pads thereon attached to the first side of the interposer. Second interconnects couple respective conductive traces to respective contact pads on the workpiece.

摘要翻译： 集成电路（IC）装置包括具有第一侧，第二侧和内孔的电介质基板的插入件，其中多个导电迹线位于第一侧。 IC芯片包括具有有源电路和底部表面的顶侧半导体表面，其中顶侧半导体表面包括多个接合焊盘，并且在内孔附接到插入件上。 第一引线键互连将各个接合焊盘耦合到相应的导电迹线。 工件包括顶部工件表面，其包括附接到插入件的第一侧上的多个接触焊盘。 第二互连将相应的导电迹线耦合到工件上的相应接触焊盘。

公开(公告)号：US20120052627A1

公开(公告)日：2012-03-01

申请号：US13052144

申请日：2011-03-21

申请人： Yukio KATAMURA ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

发明人： Yukio KATAMURA ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

IPC分类号： H01L21/50

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/27312 ,  H01L2224/27418 ,  H01L2224/27848 ,  H01L2224/29 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device including a semiconductor chip having electrode pads formed on a first major surface and a bonding layer provided on a second major surface, and a substrate having the semiconductor chip mounted on the substrate. The manufacturing method can include applying a fillet-forming material to a portion contacting an outer edge of the second major surface of the semiconductor chip on a front face of the substrate. The method can include bonding the second major surface of the semiconductor chip to the substrate via the bonding layer.

摘要翻译： 根据一个实施例，公开了一种用于制造半导体器件的方法，该半导体器件包括具有形成在第一主表面上的电极焊盘和设置在第二主表面上的接合层的半导体芯片，以及具有安装在该衬底上的半导体芯片的衬底。 制造方法可以包括在基板的前表面上将接合成形材料的半导体芯片的第二主表面的外边缘接触的部分。 该方法可以包括通过接合层将半导体芯片的第二主表面接合到衬底。

公开(公告)号：US20110279717A1

公开(公告)日：2011-11-17

申请号：US13086830

申请日：2011-04-14

申请人： Satoru Wakiyama ,  Hiroshi Ozaki

发明人： Satoru Wakiyama ,  Hiroshi Ozaki

IPC分类号： H04N5/335 ,  H01L31/18 ,  H01L31/0216

CPC分类号： H01L27/14636 ,  H01L21/56 ,  H01L21/563 ,  H01L23/31 ,  H01L24/05 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L27/14605 ,  H01L27/14609 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14634 ,  H01L27/14683 ,  H01L27/1469 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83104 ,  H01L2224/83365 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

摘要： Disclosed herein is a semiconductor device including: a first semiconductor chip having an electronic circuit section and a first connecting section formed on one surface thereof; a second semiconductor chip having a second connecting section formed on one surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the first and the second connecting sections connected to each other by a bump; a dam formed to fill a gap between the first and the second semiconductor chips on a part of an outer edge of the second semiconductor chip, the part of the outer edge being on a side of a region of formation of the electronic circuit section; and an underfill resin layer filled into the gap, protrusion of the resin layer from the outer edge of the second semiconductor chip to a side of the electronic circuit section being prevented by the dam.

摘要翻译： 本发明公开了一种半导体器件，包括：具有电子电路部分的第一半导体芯片和在其一个表面上形成的第一连接部分; 具有在其一个表面上形成的第二连接部分的第二半导体芯片，所述第二半导体芯片安装在所述第一半导体芯片上，所述第一和第二连接部分通过凸块相互连接; 形成为在所述第二半导体芯片的外缘的一部分上填充所述第一和第二半导体芯片之间的间隙的坝，所述外边缘的一部分位于所述电子电路部的形成区域的一侧; 并且填充到间隙中的底部填充树脂层，树脂层从第二半导体芯片的外边缘突出到电子电路部分的侧面被大坝阻止。

公开(公告)号：US20110057296A1

公开(公告)日：2011-03-10

申请号：US12555646

申请日：2009-09-08

申请人： CHIEN-TE FENG ,  KAZUAKI ANO ,  FRANK YU ,  TREVOR LIU

发明人： CHIEN-TE FENG ,  KAZUAKI ANO ,  FRANK YU ,  TREVOR LIU

IPC分类号： H01L23/495 ,  H01L21/78 ,  H01L23/00 ,  H05K3/20

CPC分类号： H01L29/0657 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/29035 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48475 ,  H01L2224/4848 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85051 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10156 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/35121 ,  Y10T29/49128 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ≧5% less than a cross sectional area of the top surface to provide a protruding lip having a bottom lip surface. A package substrate includes a top substrate surface including substrate bonding sites, a bottom substrate surface, and a die support structure on the top substrate surface having a gap region. The bottom lip surface of the IC die is secured to the die support structure and the bottom surface of the IC die extends below the die support structure into the gap region. Coupling connectors couple the bonding features on the IC die to the substrate bonding sites.

摘要翻译： 封装的电子器件包括厚度形状的IC管芯，其包括顶部，顶面，有源电路，底部和底面。 底面的横截面积比顶面的截面积小5％以提供具有底唇表面的突出唇缘。 封装衬底包括顶部衬底表面，其包括衬底结合部位，底部衬底表面以及具有间隙区域的顶部衬底表面上的管芯支撑结构。 IC芯片的底部唇表面固定到模具支撑结构，并且IC芯片的底表面在模具支撑结构的下方延伸到间隙区域中。 耦合连接器将IC芯片上的结合特征耦合到基板结合位置。

公开(公告)号：US07879711B2

公开(公告)日：2011-02-01

申请号：US11563973

申请日：2006-11-28

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Jean Wang

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Jean Wang

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/14051 ,  H01L2224/14135 ,  H01L2224/14155 ,  H01L2224/14179 ,  H01L2224/17517 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29035 ,  H01L2224/29075 ,  H01L2224/29116 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/29169 ,  H01L2224/29184 ,  H01L2224/29186 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81193 ,  H01L2224/83193 ,  H01L2224/9202 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12041 ,  H01L2924/14 ,  Y10S438/926 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/049 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor gate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure; forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure; bonding the first substrate with a second substrate; removing at least a portion of the first dummy structure, thereby forming a first opening; and forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.

摘要翻译： 一种方法包括：在第一衬底和第一衬底内的至少一个第一虚拟结构之上形成晶体管栅极; 在所述栅极晶体管上形成层间电介质层（ILD）层，所述ILD层包括形成在其中的至少一个接触结构，并与所述晶体管栅极形成电接触;以及至少一个第一导电结构，其至少部分地形成在所述虚拟 结构体; 在所述ILD层上形成钝化层，所述钝化层包括形成在其中并与所述导电结构电接触的至少一个第一焊盘结构; 用第二衬底接合第一衬底; 去除所述第一虚设结构的至少一部分，从而形成第一开口; 以及在所述第一开口内形成导电材料以形成第二导电结构，所述第二导电结构电耦合到所述第一导电结构。

公开(公告)号：US20050139389A1

公开(公告)日：2005-06-30

申请号：US11066153

申请日：2005-02-28

申请人： Tsuyoshi Yamamoto ,  Mitsuo Suehiro ,  Hiroshi Yamada

发明人： Tsuyoshi Yamamoto ,  Mitsuo Suehiro ,  Hiroshi Yamada

IPC分类号： H01L29/78 ,  H01L21/60 ,  H05K3/30 ,  H05K3/34 ,  H05K1/18

CPC分类号： H05K3/305 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/73103 ,  H01L2224/73204 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/0129 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0182 ,  H05K2203/0475 ,  H05K2203/1105 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49169 ,  H01L2924/00012

摘要： When an electronic component is mounted on a substrate, the electronic component is first placed on the substrate with a solid support interposed between the electronic component and the substrate. The solid support serves to space a terminal conductor of the electronic component from a corresponding terminal pad on the substrate. A conductive bonding material is then melted on the terminal pad. The melted conductive bonding material gets exposed to the peripheral atmosphere over a larger area. Even if a bubble is generated within the melted conductive bonding material, the bubble is allowed to easily get out of the melted conductive bonding material. Removal of the gas is promoted in the melted conductive bonding material. The solid support is subsequently melted. The electronic component is moved down toward the substrate, thereby contacting the terminal conductor with the melted conductive bonding material on the corresponding terminal pad. Removal of the gas in this manner leads to improvement in the strength of bonding between the substrate and the electronic component.

摘要翻译： 当将电子部件安装在基板上时，首先将电子部件放置在基板上，并将固体支撑体插入在电子部件和基板之间。 固体支撑件用于将电子部件的端子导体从衬底上的对应的端子焊盘放置。 导电接合材料然后在端子焊盘上熔化。 熔融的导电接合材料在较大的面积上暴露于周围的气氛。 即使在熔融的导电接合材料内产生气泡，也允许气泡容易地从熔融的导电接合材料中脱出。 在熔融的导电接合材料中促进除去气体。 固体支持物随后熔化。 电子部件朝向基板移动，从而使端子导体与相应的端子焊盘上的熔融的导电接合材料接触。 以这种方式去除气体导致基板和电子部件之间的结合强度的改善。

公开(公告)号：US20040095501A1

公开(公告)日：2004-05-20

申请号：US10609773

申请日：2003-06-27

申请人： KYOCERA CORPORATION

发明人： Mitsuaki Aizawa ,  Hiroki Itoh ,  Masanobu Nakai

IPC分类号： H04N005/225

CPC分类号： H04N5/2253 ,  H01L27/14618 ,  H01L27/14625 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/14135 ,  H01L2224/17051 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2924/00014 ,  H04N5/2254 ,  H04N5/2257 ,  H05K1/0219 ,  H05K3/323 ,  H05K2201/09809 ,  H05K2201/10719 ,  H05K2201/10977 ,  H01L2924/00012 ,  H01L2224/05599

摘要： An IR cut-filter is fitted into a support portion within the optical-system containing portion of a ceramic board and a lens 11 is mounted in the ceramic board by screwing the lens. In an imaging-device containing portion, an imaging device with a light receiving portion arranged therein is mounted outside the support portion by flip-chip packaging. Further, the vicinity of the flip-chip packaging portion is sealed with resin. Additionally, on the base of the imaging-device containing portion of a ceramic package, the lands of an imaging device are so positioned as to correspond to the respective land positions of a ceramic package and patterns are electrically connected by melting a gold bump, whereby the imaging device is mounted by bare-chip packaging. The land portion is filled with an underfill agent and then sheet glass is mounted on a through-hole 5b and sealed with a sealing agent, so that the through-hole 5b for containing a light receiving portion is sealed up.

摘要翻译： 将IR截止滤光片安装在陶瓷板的光学系统容纳部分内的支撑部分中，透镜11通过旋转透镜安装在陶瓷板中。 在成像装置容纳部分中，其中布置有光接收部分的成像装置通过倒装芯片封装安装在支撑部分的外部。 此外，倒装芯片封装部分附近用树脂密封。 此外，在陶瓷封装的成像装置容纳部分的基础上，成像装置的焊盘被定位成对应于陶瓷封装的各个焊盘位置，并且通过熔化金凸块来电连接图案，由此 成像装置通过裸芯片封装安装。 地面填充有底部填充剂，然后将平板玻璃安装在通孔5b上并用密封剂密封，使得用于容纳光接收部分的通孔5b被密封。