公开(公告)号：US09236363B2

公开(公告)日：2016-01-12

申请号：US14204340

申请日：2014-03-11

申请人： Jeffrey K. Jones ,  Basim H. Noori ,  Mohd Salimin Sahludin ,  Fernando A. Santos

发明人： Jeffrey K. Jones ,  Basim H. Noori ,  Mohd Salimin Sahludin ,  Fernando A. Santos

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L27/06 ,  H01L27/07 ,  H01L21/822 ,  H01L23/64 ,  H01L49/02

CPC分类号： H01L24/48 ,  H01L21/822 ,  H01L22/14 ,  H01L23/642 ,  H01L23/647 ,  H01L24/43 ,  H01L24/45 ,  H01L27/0676 ,  H01L27/0794 ,  H01L28/20 ,  H01L2224/05578 ,  H01L2224/05599 ,  H01L2224/13028 ,  H01L2224/1613 ,  H01L2224/438 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4801 ,  H01L2224/48011 ,  H01L2224/4813 ,  H01L2224/4847 ,  H01L2224/85399 ,  H01L2224/85423 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/20658 ,  H01L2924/30107 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756

摘要： A semiconductor device includes a substrate, first and second bond pad structures supported by the substrate and spaced from one another by a gap, and a wire bond foot jumper extending across the gap and bonded to the first and second bond pad structures.

摘要翻译： 半导体器件包括衬底，由衬底支撑并且通过间隙彼此间隔开的第一和第二接合焊盘结构，以及跨越间隙延伸并结合到第一和第二接合焊盘结构的引线接合脚跨接件。

公开(公告)号：US09219029B2

公开(公告)日：2015-12-22

申请号：US13326806

申请日：2011-12-15

申请人： Byung Tai Do ,  Arnel Senosa Trasporto ,  Linda Pei Ee Chua

发明人： Byung Tai Do ,  Arnel Senosa Trasporto ,  Linda Pei Ee Chua

IPC分类号： H01L29/40 ,  H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49582 ,  H01L21/4821 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/17106 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48011 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/45099 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead top side; forming a lower interior conductive layer directly on the lead top side; forming an interior insulation layer directly on the lower interior conductive layer; forming an upper interior conductive layer directly on the interior insulation layer; and mounting an integrated circuit over the upper interior conductive layer.

摘要翻译： 一种集成电路封装系统的制造方法，包括：形成具有引线顶侧的引线; 在引线顶侧直接形成下部内部导电层; 直接在下部内部导电层上形成内部绝缘层; 在内部绝缘层上直接形成上部内部导电层; 并将集成电路安装在上部内导电层上。

公开(公告)号：US08970020B2

公开(公告)日：2015-03-03

申请号：US14348602

申请日：2012-06-18

申请人： Keiji Okumura

发明人： Keiji Okumura

IPC分类号： H01L23/495 ,  H01L27/06 ,  H01L25/04 ,  H01L25/18 ,  H01L23/00

CPC分类号： H01L25/072 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/04 ,  H01L25/18 ,  H01L27/0629 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48138 ,  H01L2224/48139 ,  H01L2224/48157 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48471 ,  H01L2224/4903 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/85423 ,  H01L2224/85447 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/2065 ,  H01L2924/20651 ,  H01L2924/00015 ,  H01L2924/00012

摘要： Provided is a semiconductor device which includes a bonding wire, one end of which is connected to a bipolar device, the other end of which is connected to a conductive member, and the center of which is connected to a unipolar device, said semiconductor device being capable of improving the reliability of wire bonding. A package (4) includes a die pad (61), a source lead (63), a first MOSFET (11), and a first Schottky barrier diode (21). A source electrode (11S) of the first MOSFET (11), an anode electrode (21A) of the first Schottky barrier diode (21), and the source lead (63) are electrically connected by the bonding wire (31), one end of which is bonded to the source electrode (11S) of the first MOSFET (11), the other end of which is bonded to the source lead (63), and the center of which is bonded to the anode electrode (21A) of the first Schottky barrier diode (21).

摘要翻译： 提供一种半导体器件，其包括接合线，其一端连接到双极器件，其另一端连接到导电构件，并且其中心连接到单极器件，所述半导体器件为 能够提高引线接合的可靠性。 封装（4）包括管芯焊盘（61），源极引线（63），第一MOSFET（11）和第一肖特基势垒二极管（21）。 第一MOSFET（11）的源电极（11S），第一肖特基势垒二极管（21）的阳极电极（21A）和源极引线（63）通过接合线（31）电连接，一端 其结合到第一MOSFET（11）的源电极（11S），其另一端与源极（63）接合，并且其中心与第一MOSFET（11）的阳极电极（21A）接合， 第一肖特基势垒二极管（21）。

公开(公告)号：US20140332878A1

公开(公告)日：2014-11-13

申请号：US14340198

申请日：2014-07-24

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki SHIRAISHI ,  Tomoaki UNO ,  Nobuyoshi MATSUURA

IPC分类号： H01L29/78 ,  H02M7/00 ,  H01L23/495

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

摘要翻译： 在具有功率MOS·FET高侧开关和功率MOS·FET低侧开关串联的电路的非绝缘DC-DC转换器中，功率MOS·FET低侧开关和肖特基 与功率MOS·FET低侧开关并联连接的二极管形成在一个半导体芯片内。 肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中央，并且在其两侧设置功率MOS·FET低侧开关的形成区域。 从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

公开(公告)号：US08742258B2

公开(公告)日：2014-06-03

申请号：US13384819

申请日：2010-07-16

申请人： Shinichi Terashima ,  Tomohiro Uno ,  Takashi Yamada ,  Daizo Oda

发明人： Shinichi Terashima ,  Tomohiro Uno ,  Takashi Yamada ,  Daizo Oda

IPC分类号： H01B5/00

CPC分类号： C22C5/04 ,  C22C5/02 ,  C22C5/06 ,  C22C9/00 ,  H01L24/43 ,  H01L24/45 ,  H01L2224/05624 ,  H01L2224/4312 ,  H01L2224/4321 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/4516 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48011 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/4851 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48764 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48864 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85207 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2224/85564 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/01034 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0102 ,  H01L2924/01013 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2924/01204 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/01001 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01007 ,  H01L2224/45669 ,  H01L2924/2076 ,  H01L2924/01018 ,  H01L2224/48465 ,  H01L2924/20654 ,  H01L2924/20652 ,  H01L2924/20655 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/01004 ,  H01L2924/01033

摘要： A bonding wire for semiconductor includes: a core wire of copper or a copper alloy; a coating layer containing palladium and having a thickness of 10 to 200 nm; and an alloy layer formed on a surface of the coating layer. The alloy layer contains a noble metal and palladium and having a thickness of 1 to 80 nm. The noble metal is either gold or silver, and a concentration of the noble metal in the alloy layer is not less than 10% and not more than 75% by volume.

摘要翻译： 用于半导体的接合线包括：铜或铜合金的芯线; 含有钯的涂层，其厚度为10〜200nm; 以及形成在所述涂层的表面上的合金层。 合金层含有贵金属和钯，厚度为1〜80nm。 贵金属为金或银，合金层中贵金属的浓度为10体积％以上且75体积％以下。

公开(公告)号：US20130307138A1

公开(公告)日：2013-11-21

申请号：US13950912

申请日：2013-07-25

申请人： Tessera, Inc.

发明人： Richard Dewitt Crisp ,  Belgacem Haba ,  Wael Zohni

IPC分类号： H01L23/48

CPC分类号： H01L23/48 ,  G11C5/06 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/29 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48011 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15786 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A microelectronic package may have a plurality of terminals disposed at a face thereof which are configured for connection to at least one external component. e.g., a circuit panel. First and second microelectronic elements can be affixed with packaging structure therein. A first electrical connection can extend from a respective terminal of the package to a corresponding contact on the first microelectronic element, and a second electrical connection can extend from the respective terminal to a corresponding contact on the second microelectronic element, the first and second connections being configured such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto.

摘要翻译： 微电子封装可以具有设置在其面上的多个端子，其被配置为连接到至少一个外部部件。 例如电路板。 第一和第二微电子元件可以用其中的包装结构固定。 第一电连接可以从封装的相应端子延伸到第一微电子元件上的相应触点，并且第二电连接可以从相应端子延伸到第二微电子元件上的相应触点，第一和第二连接是 被配置为使得由每个组中的第一和第二连接承载的相应信号在相应的终端和与其耦合的每个对应的触点之间经历相同持续时间的传播延迟。

公开(公告)号：US08525313B2

公开(公告)日：2013-09-03

申请号：US13418201

申请日：2012-03-12

申请人： Binneg Y. Lao ,  William W. Chen

发明人： Binneg Y. Lao ,  William W. Chen

IPC分类号： H01L23/495

CPC分类号： H01L23/66 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/642 ,  H01L24/48 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32245 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands.

摘要翻译： 芯片组件包括芯片，桨，接口层，频率扩展器件和焊盘。 芯片有触点。 界面层设置在芯片和桨之间。 所述频率扩展装置至少具有导电层和电介质层。 导电层具有导电迹线。 频率延伸装置邻近芯片的一侧设置并且覆盖在桨上。 土地被设置在桨的侧面附近。 触点连接到导电迹线。 导电迹线连接到焊盘。 频率扩展装置被配置为减小阻抗不连续性，使得由频率延伸装置产生的阻抗不连续性小于由接合线产生的阻抗不连续性，每个接合线的长度大于或基本上等于触点之间的距离， 土地

公开(公告)号：US08502390B2

公开(公告)日：2013-08-06

申请号：US13306068

申请日：2011-11-29

申请人： Richard Dewitt Crisp ,  Belgacem Haba ,  Wael Zohni

发明人： Richard Dewitt Crisp ,  Belgacem Haba ,  Wael Zohni

IPC分类号： H01L29/40

CPC分类号： H01L23/48 ,  G11C5/06 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/29 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48011 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15786 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A microelectronic package may have a plurality of terminals disposed at a face thereof which are configured for connection to at least one external component. e.g., a circuit panel. First and second microelectronic elements can be affixed with packaging structure therein. A first electrical connection can extend from a respective terminal of the package to a corresponding contact on the first microelectronic element, and a second electrical connection can extend from the respective terminal to a corresponding contact on the second microelectronic element, the first and second connections being configured such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto.

摘要翻译： 微电子封装可以具有设置在其面上的多个端子，其被配置为连接到至少一个外部部件。 例如电路板。 第一和第二微电子元件可以用其中的包装结构固定。 第一电连接可以从封装的相应端子延伸到第一微电子元件上的相应触点，并且第二电连接可以从相应端子延伸到第二微电子元件上的相应触点，第一和第二连接是 被配置为使得由每个组中的第一和第二连接承载的相应信号在相应的终端和与其耦合的每个对应的触点之间经历相同持续时间的传播延迟。

公开(公告)号：US20120306020A1

公开(公告)日：2012-12-06

申请号：US13588538

申请日：2012-08-17

申请人： Masaki SHIRAISHI ,  Tomoaki UNO ,  Nobuyoshi MATSUURA

发明人： Masaki SHIRAISHI ,  Tomoaki UNO ,  Nobuyoshi MATSUURA

IPC分类号： H01L27/088

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

公开(公告)号：US08247911B2

公开(公告)日：2012-08-21

申请号：US12445789

申请日：2008-01-15

申请人： Tomohiro Uno ,  Shinichi Terashima ,  Keiichi Kimura ,  Takashi Yamada ,  Akihito Nishibayashi

发明人： Tomohiro Uno ,  Shinichi Terashima ,  Keiichi Kimura ,  Takashi Yamada ,  Akihito Nishibayashi

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L24/78 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/4312 ,  H01L2224/4321 ,  H01L2224/43821 ,  H01L2224/43825 ,  H01L2224/43826 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4556 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/45669 ,  H01L2224/45673 ,  H01L2224/48011 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/781 ,  H01L2224/78268 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85186 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01204 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/01001 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2224/45655 ,  H01L2224/45657 ,  H01L2224/45671 ,  H01L2224/45666 ,  H01L2924/20652 ,  H01L2924/20655 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2924/013 ,  H01L2924/2075 ,  H01L2924/01049 ,  H01L2924/01006

摘要： Provided is a bonding structure of a bonding wire and a method for forming the same which can solve problems of conventional technologies in practical application of a multilayer copper wire, improve the formability and bonding characteristic of a ball portion, improve the bonding strength of wedge connection, and have a superior industrial productivity. A bonding wire mainly composed of copper, and a concentrated layer where the concentration of a conductive metal other than copper is high is formed at a ball bonded portion. The concentrated layer is formed in the vicinity of the ball bonded portion or at the interface thereof. An area where the concentration of the conductive metal is 0.05 to 20 mol % has a thickness greater than or equal to 0.1 μm, and it is preferable that the concentration of the conductive metal in the concentrated layer should be five times as much as the average concentration of the conductive metal at the ball bonded portion other than the concentrated layer.

摘要翻译： 提供一种接合线的接合结构及其形成方法，其可以解决多层铜线的实际应用中的现有技术的问题，提高球部的成形性和接合特性，提高楔连接的接合强度 ，具有较高的工业生产率。 主要由铜构成的接合线以及铜以外的导电性金属的浓度高的浓缩层形成在球接合部。 浓缩层形成在球接合部分附近或其界面处。 导电性金属的浓度为0.05〜20摩尔％的区域的厚度大于等于0.1微米，并且浓缩层中的导电性金属的浓度优选为平均浓度的5倍 导电金属在浓缩层以外的球接合部分的浓度。