公开(公告)号：US08581387B1

公开(公告)日：2013-11-12

申请号：US13771440

申请日：2013-02-20

Applicant: Micron Technology, Inc.

Inventor： David R. Hembree ,  Alan G. Wood

IPC: H01L23/04

CPC classification number: H01L24/16 ,  G01R1/06716 ,  G01R1/07307 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02125 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/0333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/45116 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45655 ,  H01L2224/45684 ,  H01L2224/45698 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48455 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/4899 ,  H01L2224/48992 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/10155 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45164 ,  H01L2924/013 ,  H01L2924/00013

Abstract: A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from a first side to a second side thereof, and a wire in the via electrically insulated from the semiconductor substrate having a first end with a bonded connection to the substrate contact and a second end proximate to the second side of the semiconductor substrate. The through wire interconnect also includes a first contact on the wire proximate to the first side of the semiconductor substrate, a second contact on the second end of the wire, and a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed. The through wire interconnect can also include a bonding member bonded to the first end of the wire and to the substrate contact having a tip portion forming the first contact.

Abstract translation: 用于半导体衬底的通线互连包括从第一侧延伸穿过半导体衬底到第二侧的通孔以及与半导体衬底电绝缘的通孔中的导线，该第一端具有与衬底接触的接合连接 以及靠近半导体衬底的第二侧的第二端。 通线互连还包括靠近半导体衬底的第一侧的导线上的第一接触件，线的第二端上的第二接触件和第一侧上的至少部分地封装电线的聚合物层，同时留下 第一接触暴露。 通线互连还可以包括接合到线的第一端的接合构件和具有形成第一接触的尖端部分的衬底接触。

公开(公告)号：US20130136898A1

公开(公告)日：2013-05-30

申请号：US13751671

申请日：2013-01-28

Applicant: Micron Technology, Inc.

Inventor： David Pratt ,  David R. Hembree

IPC: H05K13/00

CPC classification number: H01L24/94 ,  B23B7/02 ,  B32B3/30 ,  B32B7/02 ,  B32B7/14 ,  B32B37/1292 ,  B32B37/144 ,  H01L21/78 ,  H01L24/83 ,  H01L2924/14 ,  H05K13/00 ,  Y10T156/19 ,  Y10T156/1994 ,  Y10T428/14 ,  Y10T428/24479 ,  Y10T428/24521 ,  Y10T428/24562 ,  Y10T428/24612 ,  Y10T428/24752 ,  Y10T428/24802 ,  Y10T428/24851 ,  Y10T428/24942 ,  H01L2924/00

Abstract: Methods and apparatuses for releasably attaching support members to microfeature workpieces to support members are disclosed herein. In one embodiment, for example, a method for processing a microfeature workpiece including a plurality of microelectronic dies comprises forming discrete blocks of material at a first side of a support member. The blocks are arranged on the support member in a predetermined pattern. The method also includes depositing an adhesive material into gaps between the individual blocks of material and placing a first side of the workpiece in contact with the adhesive material and/or the blocks. The method further includes cutting through a second side of the workpiece to singulate the dies and to expose at least a portion of the adhesive material in the gaps. The method then includes removing at least approximately all the adhesive material from the support member and/or the workpiece with a solvent.

公开(公告)号：US20240055411A1

公开(公告)日：2024-02-15

申请号：US18486950

申请日：2023-10-13

Applicant: Micron Technology, Inc.

Inventor： Travis M. Jensen ,  David R. Hembree

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06586

Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.

公开(公告)号：US10461059B2

公开(公告)日：2019-10-29

申请号：US15007615

申请日：2016-01-27

Applicant: Micron Technology, Inc.

Inventor： Michel Koopmans ,  Shijian Luo ,  David R. Hembree

IPC: H01L23/02 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/373 ,  H01L23/522 ,  H01L23/367 ,  H01L23/498

Abstract: Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. A package substrate carries the thermally conductive casing, and an interposer is disposed between the thermally conductive casing and the stack of semiconductor dies. A peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies and is coupled to a plurality of conductive members interposed between the peripheral portion and the package substrate.

公开(公告)号：US10163755B2

公开(公告)日：2018-12-25

申请号：US15498321

申请日：2017-04-26

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L21/52 ,  H01L21/54 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/44 ,  H01L25/00 ,  H01L25/18 ,  H01L23/053 ,  H01L23/367 ,  H01L23/373

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US20170229439A1

公开(公告)日：2017-08-10

申请号：US15498321

申请日：2017-04-26

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/373 ,  H01L23/00 ,  H01L23/44 ,  H01L25/18 ,  H01L23/367

CPC classification number: H01L23/44 ,  H01L21/50 ,  H01L21/52 ,  H01L21/54 ,  H01L21/563 ,  H01L23/04 ,  H01L23/053 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/3736 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/156 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US20160141270A1

公开(公告)日：2016-05-19

申请号：US15007615

申请日：2016-01-27

Applicant: Micron Technology, Inc.

Inventor： Michel Koopmans ,  Shijian Luo ,  David R. Hembree

IPC: H01L25/065 ,  H01L23/373 ,  H01L25/00 ,  H01L23/522

CPC classification number: H01L25/0652 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5226 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/01047

Abstract: Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. A package substrate carries the thermally conductive casing, and an interposer is disposed between the thermally conductive casing and the stack of semiconductor dies. A peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies and is coupled to a plurality of conductive members interposed between the peripheral portion and the package substrate.

公开(公告)号：US08669179B2

公开(公告)日：2014-03-11

申请号：US13940034

申请日：2013-07-11

Applicant: Micron Technology, Inc.

Inventor： Salman Akram ,  Charles M. Watkins ,  William M. Hiatt ,  David R. Hembree ,  James M. Wark ,  Warren M. Farnworth ,  Mark E. Tuttle ,  Sidney B. Rigg ,  Steven D. Oliver ,  Kyle K. Kirby ,  Alan G. Wood ,  Lu Velicky

IPC: H01L21/4763

CPC classification number: H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract translation: 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

公开(公告)号：US20130299983A1

公开(公告)日：2013-11-14

申请号：US13945392

申请日：2013-07-18

Applicant: Micron Technology Inc.

Inventor： Alan G. Wood ,  David R. Hembree

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L23/02 ,  B33Y70/00 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/49429 ,  H01L2224/78301 ,  H01L2224/85001 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85121 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00015 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012

Abstract: A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from the first side to the second side thereof; a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side of the semiconductor substrate; a dielectric material in the via configured to electrically insulate the wire from the semiconductor substrate; a bonding member bonded to the first end of the wire and to the substrate contact configured to secure the wire to the substrate contact; and a contact on the second end of the wire.

Abstract translation: 用于半导体衬底的通线互连包括从第一侧延伸穿过半导体衬底到第二侧的通孔; 所述通孔中的导线具有第一端，所述第一端具有与所述衬底接触的接合连接，以及靠近所述半导体衬底的第二侧的第二端; 所述通孔中的电介质材料被配置为使所述导线与所述半导体衬底电绝缘; 接合构件，其接合到所述导线的所述第一端和所述衬底接触件，被配置为将所述导线固定到所述衬底接触件; 和电线第二端的触点。

公开(公告)号：US20130234296A1

公开(公告)日：2013-09-12

申请号：US13871484

申请日：2013-04-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Owen R. Fay ,  Warren M. Farnworth ,  David R. Hembree

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05611 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1161 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13075 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13687 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81898 ,  H01L2224/831 ,  H01L2224/83141 ,  H01L2224/83193 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

Abstract translation: 公开了用于堆叠管芯的互连结构，包括贯穿硅通孔的穿透结构以及相关的系统和方法。 根据特定实施例的系统包括具有第一衬底材料的第一半导体衬底和由第一半导体衬底承载的穿透结构。 该系统还包括第二半导体衬底，该第二半导体衬底具有带有预制凹槽的第二衬底材料。 第一半导体衬底的穿透结构被容纳在第二半导体衬底的凹部中，并且与凹部机械地接合并固定到第二半导体衬底。