公开(公告)号：US20180337150A1

公开(公告)日：2018-11-22

申请号：US15980033

申请日：2018-05-15

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： You WU ,  Jun ZHU

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05124

摘要： A semiconductor device and its manufacturing method are presented. The manufacturing method includes: providing a semiconductor structure comprising: an interlayer dielectric layer, a first metal layer surrounded by the interlayer dielectric layer, and a semiconductor layer on the interlayer dielectric layer; etching the semiconductor layer to form an opening exposing the interlayer dielectric layer, wherein the opening comprises a first opening and a second opening on the first opening; forming an insulation layer on the semiconductor structure; etching the insulation layer and the interlayer dielectric layer at the bottom of the first opening to form a groove exposing a portion of the first metal layer; forming a second metal layer on the insulation layer and on the bottom and a side surface of the groove; and patterning the second metal layer. The second metal layer in this inventive concept can be removed more completely than conventional methods.

公开(公告)号：US10083928B2

公开(公告)日：2018-09-25

申请号：US15419934

申请日：2017-01-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/17 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13655 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/175 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

摘要： A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

公开(公告)号：US20180269163A1

公开(公告)日：2018-09-20

申请号：US15885837

申请日：2018-02-01

申请人： FUJI ELECTRIC CO., LTD.

发明人： Morio IWAMIZU

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/45

CPC分类号： H01L23/562 ,  H01L21/28568 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823475 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/06 ,  H01L27/0617 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03831 ,  H01L2224/03845 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48477 ,  H01L2224/48499 ,  H01L2924/04941 ,  H01L2924/13055 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01013

摘要： To protect the insulating film so that crack is not produced in the insulating film even when stress is applied to the semiconductor device. A manufacturing method of a semiconductor device is provided, including: forming an insulating film above a semiconductor substrate; forming, in the insulating film, one or more openings that expose the semiconductor substrate; forming a tungsten portion deposited in the openings and above the insulating film; thinning the tungsten portion on condition that the tungsten portion remains in at least part of a region above the insulating film; and forming an upper electrode above the tungsten portion.

公开(公告)号：US20180240766A1

公开(公告)日：2018-08-23

申请号：US15833098

申请日：2017-12-06

申请人： Murata Manufacturing Co., Ltd.

发明人： Isao OBU ,  Yasunari Umemoto ,  Masahiro Shibata

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L29/20

CPC分类号： H01L24/05 ,  H01L21/30617 ,  H01L21/3083 ,  H01L21/76898 ,  H01L23/3157 ,  H01L24/32 ,  H01L29/06 ,  H01L29/20 ,  H01L2224/0346 ,  H01L2224/04026 ,  H01L2224/05011 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05164 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/26145 ,  H01L2224/29139 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2924/10158 ,  H01L2924/1424 ,  H01L2924/35121 ,  H01L2924/00014

摘要： A compound semiconductor substrate has a first main surface parallel to a first direction and a second direction perpendicular to the first direction, a second main surface located on a side opposite to the first main surface, and a recess. The recess has an opening, a bottom surface facing the opening, and a plurality of side surfaces located between the opening and the bottom surface. The side surfaces include at least one first side surface forming an angle of about θ degrees with the bottom surface in the recess and at least one second side surface forming an angle of about ϕ degrees with the bottom surface in the recess. The total length of edge lines between the first main surface and the at least one first side surface is larger than that of edge lines between the first main surface and the at least one second side surface.

公开(公告)号：US20180226370A1

公开(公告)日：2018-08-09

申请号：US15945006

申请日：2018-04-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Jung Yang ,  Hsien-Wei Chen ,  Hsien-Ming Tu ,  Chang-Pin Huang ,  Yu-Chia Lai ,  Tung-Liang Shao

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L21/76802 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/02311 ,  H01L2224/02351 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0346 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05563 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/73204 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00

摘要： A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

公开(公告)号：US20180212028A1

公开(公告)日：2018-07-26

申请号：US15878143

申请日：2018-01-23

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Takashi KUNO ,  Hiroki TSUMA ,  Satoshi KUWANO ,  Akitaka SOENO ,  Toshitaka KANEMARU ,  Kenta HASHIMOTO ,  Noriyuki KAKIMOTO ,  Shuji YONEDA

IPC分类号： H01L29/417 ,  H01L23/31 ,  H01L23/00 ,  H01L21/285 ,  H01L29/45 ,  H01L29/739 ,  H01L29/66

CPC分类号： H01L29/41708 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/32133 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/53223 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L29/0696 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66348 ,  H01L29/7397 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05018 ,  H01L2224/05076 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05224 ,  H01L2224/05347 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01014

摘要： A semiconductor device may include: a semiconductor substrate; a surface electrode covering a surface of the semiconductor substrate; an insulating protection film covering a part of a surface of the surface electrode; and a solder-bonding metal film, the solder-bonding metal film covering a range spreading from a surface of the insulating protection film to the surface of the surface electrode, wherein the surface electrode may include: a first metal film provided on the semiconductor substrate; a second metal film being in contact with a surface of the first metal film, and having tensile strength higher than tensile strength of the first metal film; and a third metal film being in contact with a surface of the second metal film, and having tensile strength which is lower than the tensile strength of the second metal film and is higher than the tensile strength of the first metal film.

公开(公告)号：US09997497B2

公开(公告)日：2018-06-12

申请号：US15485104

申请日：2017-04-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Wen-Chih Chiou ,  Fang Wen Tsai ,  Chen-Yu Tsai

IPC分类号： H01L25/065 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L21/0217 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76871 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2224/05552

摘要： A device includes a through substrate via (TSV) extending through a device substrate. The TSV includes a first conductive material having a sidewall, a protruding end of the TSV protruding from a second side of the device substrate. A liner covers the sidewall of the first conductive material from a below the top surface of the protruding end of the TSV to an opposite end of the TSV. A passivation layer is disposed over the second side of the device substrate and over a portion of the liner disposed on the protruding end of the TSV, the passivation layer having a stair-step surface extending away from the TSV. A conductive interface layer is disposed over the passivation layer, the sidewall of the first conductive material, and the top surface of the protruding end of the TSV. A second conductive material is disposed over the first conductive material.

公开(公告)号：US09859235B2

公开(公告)日：2018-01-02

申请号：US12619503

申请日：2009-11-16

申请人： Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Shin-Puu Jeng ,  Ying-Ju Chen ,  Shang-Yun Hou ,  Pei-Haw Tsao ,  Chen-Hua Yu

发明人： Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Shin-Puu Jeng ,  Ying-Ju Chen ,  Shang-Yun Hou ,  Pei-Haw Tsao ,  Chen-Hua Yu

IPC分类号： H01L23/488 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/05 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0215 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05566 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2924/2064 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.

公开(公告)号：US09768135B2

公开(公告)日：2017-09-19

申请号：US14972049

申请日：2015-12-16

申请人： Monolithic Power Systems, Inc.

发明人： Ze-Qiang Yao ,  Fayou Yin ,  Xiaodan Shang

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/13 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05087 ,  H01L2224/05096 ,  H01L2224/05548 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/10145 ,  H01L2224/1147 ,  H01L2224/119 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/35121 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2224/0346 ,  H01L2224/1146 ,  H01L2224/034 ,  H01L2224/114

摘要： The present disclosure discloses a semiconductor device having conductive bumps formed on a conductive redistribution layer and associated method for manufacturing. The semiconductor device may further include a first type shallow trench formed on a passivation layer overlying a semiconductor substrate. The conductive redistribution layer is formed in the first type shallow trench. A polyimide layer may be formed between neighboring conductive redistribution layers should a plurality of the conductive redistribution layers are formed with or without the first type shallow trench formed for each of the plurality of conductive redistribution layers.

公开(公告)号：US20170194283A1

公开(公告)日：2017-07-06

申请号：US15385653

申请日：2016-12-20

申请人： IMEC VZW ,  Katholieke Universiteit Leuven

发明人： Vikas Dubey ,  Eric Beyne ,  Jaber Derakhshandeh

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498

CPC分类号： H01L24/81 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/0601 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13009 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13541 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16058 ,  H01L2224/16112 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/8114 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/01049 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01005 ,  H01L2924/206 ,  H01L2924/20106 ,  H01L2924/207

摘要： A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.