Microelectronic assemblies having very fine pitch stacking
    42.
    发明申请
    Microelectronic assemblies having very fine pitch stacking 有权
    微电子组件具有非常细的间距堆积

    公开(公告)号:US20070148819A1

    公开(公告)日:2007-06-28

    申请号:US11318164

    申请日:2005-12-23

    IPC分类号: H01L21/00 H01L21/44

    摘要: A microelectronic assembly includes two or more microelectronic packages stacked at a fine pitch, which is finer than the pitch that is possible when using solder balls for making the joint. Each stackable package desirably includes a substrate having pins projecting from one surface of the substrate and solder balls projecting from the other surface of the substrate. Each stackable package may have one or more die attached to one or more of the surfaces of the substrate. In certain embodiments, die may be attached to both surfaces of the substrate. The dies may be electrically interconnected with the substrate using wire bonds, flip chip bonding, leads and/or stud bumping. The die may be encapsulated in an encapsulated material, under-filled or glob topped. In certain preferred embodiments, the combination of the conductive post height and ball height is equal to or greater than the height of the encapsulated or molded chip structure. The combination of the conductive post height and the ball height must be at least equal to the height of the encapsulated chip structure so that the conductive elements are able to span the gap between layers of the assembly. After the tips of the conductive pads are in contact with the solder masses, the solder masses are reflowed to form a permanent electrical interconnection between the stacked microelectronic packages. During reflow, the reflowed solder will wick up around the conductive posts to form elongated solder columns. In addition, when the solder is reflowed, surface tension pulls the opposing layers of the assembly toward one another and provides a self-centering action for the conductive posts.

    摘要翻译: 微电子组件包括以细间距堆叠的两个或更多个微电子封装,其比使用用于制造接头的焊球可能的间距更细。 每个可堆叠封装理想地包括具有从基板的一个表面突出的销和从该基板的另一个表面突出的焊球的基板。 每个可堆叠的封装可以具有一个或多个管芯附接到衬底的一个或多个表面。 在某些实施例中,管芯可以附接到衬底的两个表面。 模具可以使用引线接合,倒装芯片接合,引线和/或螺柱凸起与基板电互连。 芯片可以封装在封装的材料中,未充满的或者顶部的。 在某些优选实施例中,导电柱高度和球高度的组合等于或大于封装或模制芯片结构的高度。 导电柱高度和球高度的组合必须至少等于封装的芯片结构的高度,使得导电元件能够跨越组件的层之间的间隙。 在导电焊盘的尖端与焊料块接触之后,焊料质量被回流以在堆叠的微电子封装之间形成永久的电互连。 在回流期间,回流的焊料将在导电柱周围吸收,形成细长的焊料柱。 此外,当焊料回流时,表面张力将组件的相对的层相互拉向彼此,并为导电柱提供自对中动作。

    Semiconductor chip assembly
    45.
    发明授权
    Semiconductor chip assembly 有权
    半导体芯片组装

    公开(公告)号:US06169328A

    公开(公告)日:2001-01-02

    申请号:US09246056

    申请日:1999-02-08

    IPC分类号: H01L2348

    摘要: A semiconductor chip package structure for providing a reliable interface between a semiconductor chip and a PWB to accommodate for the thermal coefficient of expansion mismatch therebetween. The interface between a chip and a PWB is comprised of a package substrate having a plurality of compliant pads defining channels therebetween. The package substrate is typically comprised of a flexible dielectric sheet that has leads and terminals on at least one surface thereof. The pads have a first coefficient of thermal expansion (“CTE”) and are comprised of a material having a fairly low modulus of elasticity. An encapsulant having a second CTE lower than the CTE of the compliant pads is disposed within the channels to form a uniform encapsulation layer. The pads are in rough alignment with the conductive terminals on the package substrate thereby allowing independent movement of the terminals during thermal cycling of the chip. The encapsulant encases the conductive leads electrically connecting the terminals to chip contacts on a face surface of the chip. The lower CTE of the encapsulant controls the flexing of the conductive leads so that the leads do not prematurely fatigue and become unreliable while the lower modulus compliant pads relieve the stress on the solder balls induced by the CTE mismatch of the chip and the PWB.

    摘要翻译: 一种用于在半导体芯片和PWB之间提供可靠接口的半导体芯片封装结构,以适应其间的热膨胀系数不匹配。 芯片和PWB之间的接口包括具有多个在其间形成通道的柔性衬垫的封装衬底。 封装基板通常由在其至少一个表面上具有引线和端子的柔性电介质片构成。 垫具有第一热膨胀系数(“CTE”),并且由具有相当低的弹性模量的材料组成。 具有比柔性焊盘的CTE低的第二CTE的密封剂设置在通道内以形成均匀的封装层。 焊盘与封装衬底上的导电端子粗略对准,从而允许在芯片的热循环期间端子的独立移动。 密封剂封装导电引线,将引线电连接到芯片的表面上的芯片触点。 密封剂的较低CTE控制导电引线的弯曲,使得引线不会过早地疲劳并变得不可靠,而较低模量的柔性焊盘缓解由芯片和PWB的CTE不匹配引起的焊球上的应力。

    BSI image sensor package with variable-height silicon for even reception of different wavelengths
    47.
    发明授权
    BSI image sensor package with variable-height silicon for even reception of different wavelengths 有权
    BSI图像传感器封装,具有可变高度的硅,用于均匀接收不同的波长

    公开(公告)号:US08937361B2

    公开(公告)日:2015-01-20

    申请号:US13114243

    申请日:2011-05-24

    IPC分类号: H01L31/0232 H01L27/146

    摘要: A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a rear face. A semiconductor region has a first thickness between the first light sensing element and the rear face and a second thickness between the second light sensing element and the rear face such that the first and second light sensing elements receive light of substantially the same intensity. A dielectric region is provided at least substantially filling a space of the semiconductor region adjacent at least one of the light sensing elements. The dielectric region may include at least one light guide.

    摘要翻译: 提供了一种用于背面照明的微电子图像传感器组件及其制造方法。 该组件包括具有在正面暴露的触点的微电子元件和被布置成通过后表面接收不同波长的光的光感测元件。 半导体区域在第一光感测元件和后表面之间具有第一厚度,并且在第二光感测元件和后表面之间具有第二厚度,使得第一和第二光感测元件接收基本上相同强度的光。 提供至少基本上填充与至少一个光感测元件相邻的半导体区域的空间的电介质区域。 电介质区域可以包括至少一个光导。