公开(公告)号：US08487446B2

公开(公告)日：2013-07-16

申请号：US13095317

申请日：2011-04-27

申请人： Todd B Myers ,  Nicolas R Watts ,  Eric C Palmer ,  Jui Min Lim

发明人： Todd B Myers ,  Nicolas R Watts ,  Eric C Palmer ,  Jui Min Lim

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

摘要翻译： 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。

公开(公告)号：USRE44251E1

公开(公告)日：2013-06-04

申请号：US10839813

申请日：2004-05-06

申请人： Motoo Asai ,  Yoichiro Kawamura ,  Yoji Mori

发明人： Motoo Asai ,  Yoichiro Kawamura ,  Yoji Mori

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H01L23/49833 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01R12/523 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/114 ,  H05K3/184 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0212 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09727 ,  H05K2201/10674 ,  H05K2201/10734

摘要： A board for mounting electronic circuit parts includes a first connection terminal group including a plurality of connection terminals densely formed on the top surface of a substrate having through holes formed therein, and a second connection terminal group including a plurality of connection terminals formed at at least the peripheral portion of a back surface of the substrate. The first connection terminal group is connected to the second connection terminal group by way of the through holes. A build-up multilayer interconnection layer having via holes is formed on the top surface of the substrate, so that the first connection terminal group is connected to the second connection terminal group through the build-up multilayer interconnection layer and the through holes. According to another aspect, each signal line on the top surface of the build-up multilayer interconnection layer comprises a plurality of wiring patterns having different widths and a taper-shaped pattern that connects those wiring patterns together and whose width continuously changes. Each signal line has a smaller width at an area having a relatively high wiring density than at an area having a relatively low wiring density.

公开(公告)号：US08304662B2

公开(公告)日：2012-11-06

申请号：US11806680

申请日：2007-06-01

申请人： Akiyoshi Saitou ,  Takeshi Midorikawa ,  Toru Kuraishi ,  Chikayuki Kumagai ,  Masashi Fujimoto ,  Kenichiro Abe

发明人： Akiyoshi Saitou ,  Takeshi Midorikawa ,  Toru Kuraishi ,  Chikayuki Kumagai ,  Masashi Fujimoto ,  Kenichiro Abe

IPC分类号： H05K1/16

CPC分类号： H05K1/0224 ,  H01L2924/0002 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4661 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/0959 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2203/0425 ,  H05K2203/063 ,  Y10T29/49117 ,  H01L2924/00

摘要： A buildup board includes a buildup layer having a multilayer structure and/or a core layer having a multilayer structure. The multilayer structure includes a signal wiring pattern, a pad connected to the signal wiring pattern, an insulating part arranged around the pad on the same layer as the pad, and a conductor arranged around the insulating part on the same layer as the pad. The multilayer structure has at least two different keepouts where the keepout is defined as a minimum interval between an outline of the pad and the conductor closest to the pad on the same layer.

摘要翻译： 堆积板包括具有多层结构的堆积层和/或具有多层结构的芯层。 多层结构包括信号布线图案，连接到信号布线图案的焊盘，与焊盘相同的层上布置在焊盘周围的绝缘部分，以及布置在与焊盘相同的层上的绝缘部分周围的导体。 所述多层结构具有至少两个不同的保持部，其中所述挡板被定义为所述焊盘的轮廓与最靠近所述焊盘在同一层上的导体之间的最小间隔。

公开(公告)号：US20120273116A1

公开(公告)日：2012-11-01

申请号：US13536815

申请日：2012-06-28

申请人： Young Ho SOHN ,  Seog Moon CHOI ,  Sung Keun PARK ,  Young Ki LEE ,  Bum Sik JANG ,  Ji Hyun PARK

发明人： Young Ho SOHN ,  Seog Moon CHOI ,  Sung Keun PARK ,  Young Ki LEE ,  Bum Sik JANG ,  Ji Hyun PARK

IPC分类号： B32B38/04 ,  B32B38/08

CPC分类号： H05K3/4623 ,  H05K1/056 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4641 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096

摘要： Disclosed herein is a heat dissipating substrate having a structure in which two two-layered core substrates, each including a metal core functioning to radiate heat, are laminated and connected in parallel to each other, thus accomplishing more improved radiation performance, and a method of manufacturing the same.

摘要翻译： 本发明公开了一种散热基板，其结构是将两个分别包含发热功能的金属芯片的两层芯基板彼此并联并相互并联，从而实现更好的辐射性能， 制造相同。

公开(公告)号：US20120231179A1

公开(公告)日：2012-09-13

申请号：US13474735

申请日：2012-05-18

申请人： Cheng-Po Yu

发明人： Cheng-Po Yu

IPC分类号： H05K3/00 ,  C25D5/02 ,  B05D3/06

CPC分类号： H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

摘要： An embedded wiring board includes an upper wiring layer, a lower wiring layer, an insulation layer, a first conductive pillar and a second conductive pillar. The upper wiring layer contains an upper pad, the lower wiring layer contains a lower pad, and the insulation layer contains an upper surface and a lower surface opposite to the upper surface. The upper pad is embedded in the upper surface and the lower pad is embedded in the lower surface. The first conductive pillar is located in the insulation layer and includes an end surface which is exposed by the upper surface. A height of the first conductive pillar relative to the upper surface is larger than a depth of the upper pad relative to the upper surface. In addition, the second conductive pillar is located in the insulation layer and is connected between the first conductive pillar and the lower pad.

摘要翻译： 嵌入布线板包括上布线层，下布线层，绝缘层，第一导电柱和第二导电柱。 上布线层包含上焊盘，下布线层包含下焊盘，绝缘层包含与上表面相对的上表面和下表面。 上垫片嵌入在上表面中，下垫片嵌入下表面。 第一导电柱位于绝缘层中，并且包括由上表面暴露的端面。 第一导电柱相对于上表面的高度大于上垫相对于上表面的深度。 此外，第二导电柱位于绝缘层中并连接在第一导电柱和下垫之间。

公开(公告)号：US08232477B2

公开(公告)日：2012-07-31

申请号：US12494798

申请日：2009-06-30

申请人： Kazunori Kitamura ,  Yukihiro Koga ,  Kiyoshi Sato

发明人： Kazunori Kitamura ,  Yukihiro Koga ,  Kiyoshi Sato

IPC分类号： H05K1/03 ,  H01L23/053 ,  H01L23/12

CPC分类号： H05K3/0094 ,  C08K3/013 ,  C08K2201/003 ,  C08L63/00 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10T428/24917

摘要： In a curable resin composition containing an inorganic filler, the average particle diameter of the inorganic filler is 1 μm or less and the content of the inorganic filler is 50 wt % or less. The curable resin composition can be preferably used for a halogen-free resin substrate and the like having a small load on an environment as a hole-plugging curable resin composition as well as used to provide a hole-plugging build-up printed wiring board having a via-on-via structure (in particular, a stacked via structure) having an excellent crack-resistant property, an excellent insulation/connection reliability, and the like.

摘要翻译： 在含有无机填料的固化性树脂组合物中，无机填料的平均粒径为1μm以下，无机填料的含量为50重量％以下。 固化性树脂组合物可以优选用于作为空穴堵塞固化性树脂组合物的环境负荷小的无卤素树脂基材等，并且用于提供具有孔堵塞积聚印刷线路板，其具有 具有优异的抗裂性，优异的绝缘/连接可靠性等的通孔通孔结构（特别是堆叠通孔结构）。

公开(公告)号：US20120125680A1

公开(公告)日：2012-05-24

申请号：US13357663

申请日：2012-01-25

申请人： Naohiro Hirose ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

发明人： Naohiro Hirose ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

IPC分类号： H05K1/02 ,  C25D5/02 ,  B23K1/20 ,  B23K31/02 ,  H05K3/46 ,  C25D7/00

CPC分类号： H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 μm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be prevented. Thus, the reliability of the connection of the via holes can be improved.

摘要翻译： 通过激光束在树脂20中形成开口，从而形成通孔。 此时，通过进行蚀刻来降低导热率的铜箔22的厚度（3μm）被用作保形掩模。 因此，如果脉冲形激光束的照射次数减少，则可以在树脂20中形成开口20a。 因此，可以防止形成层间绝缘树脂层的树脂20的底切的发生。 因此，可以防止通孔的连接的可靠性。 因此，可以提高通孔连接的可靠性。

公开(公告)号：US08129625B2

公开(公告)日：2012-03-06

申请号：US10551439

申请日：2004-04-06

申请人： Shinobu Kato

发明人： Shinobu Kato

IPC分类号： H05K1/16

CPC分类号： H01L23/50 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09609 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In a core substrate 30, a ground through hole 36E and a power through hole 36P are disposed in the grid formation, so that electromotive force induced in X direction and Y direction cancel out each other. As a result, even if mutual inductance is reduced and a high frequency IC chip is loaded, electric characteristic and reliability can be improved without generating malfunction or error.

摘要翻译： 在芯基板30中，在栅格形成中设置有接地贯通孔36E和电力通孔36P，使得在X方向和Y方向上感应的电动势相互抵消。 结果，即使减小互感并且加载高频IC芯片，也可以提高电特性和可靠性而不产生故障或错误。

公开(公告)号：US20120017437A1

公开(公告)日：2012-01-26

申请号：US13252256

申请日：2011-10-04

申请人： Rabindra N. Das ,  Kostas I. Papathomas ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Kostas I. Papathomas ,  Voya R. Markovich

IPC分类号： H05K3/40

CPC分类号： H05K1/0313 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/16 ,  B23K2103/172 ,  B23K2103/52 ,  H01B1/22 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01322 ,  H01L2924/15311 ,  H05K1/097 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0257 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10378 ,  H05K2203/0425 ,  H05K2203/1152 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

摘要： A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.

摘要翻译： 一种电路化基板，包括用于提供电连接的导电浆料。 在一个实施方案中，糊状物包括包含纳米颗粒的金属组分，并且可以包括附加元素，例如焊料或其它金属微粒，以及导电聚合物和有机物。 糊料组合物的颗粒烧结并且根据添加的另外的元素而熔化，因为层压，从而形成通过糊料的有效连续的电路。 还提供了制造这种基板的方法，以及利用该基板并且包括诸如与其耦合的半导体芯片的电子部件的电组件。

公开(公告)号：US20110198723A1

公开(公告)日：2011-08-18

申请号：US13095317

申请日：2011-04-27

申请人： Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

发明人： Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

IPC分类号： H01L29/92

CPC分类号： H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

摘要翻译： 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。